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59 lines
1.0 KiB
Systemverilog
59 lines
1.0 KiB
Systemverilog
module tb_vector_abs();
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logic [31:0] a;
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logic [31:0] b;
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logic [31:0] res;
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vector_abs dut(
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.x(a),
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.y(b),
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.abs(res)
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);
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integer err_count = 0;
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task check_result(input logic [31:0]a, b, res);
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begin : check_result
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reg [31:0] ref_res;
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ref_res = a < b? a/2 + b : a + b/2;
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if (res !== ref_res) begin
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$display("Incorrect res at time %0t:", $time);
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$display("a = %0d, b = %0d", a, b);
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$display("design res = %0d", res);
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$display("reference res = %0d", ref_res);
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$display("------------------");
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err_count = err_count + 1'b1;
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end
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end
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endtask
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initial begin : test
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integer i;
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$timeformat(-9,0,"ns");
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a = 0; b = 0;
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#5;
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check_result(a,b,res);
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a = 1; b = 1;
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#5;
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check_result(a,b,res);
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a = 3; b = 4;
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#5;
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check_result(a,b,res);
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for(i = 0; i < 100; i=i+1) begin
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a = $random()&32'hff; b = $random()&32'hff;
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#5;
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check_result(a,b,res);
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end
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$display("Test has been finished with %d errors", err_count);
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if(err_count == 0) begin
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$display("SUCCESS!");
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end
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$finish();
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end
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endmodule
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