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634 lines
20 KiB
Systemverilog
634 lines
20 KiB
Systemverilog
/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Alexander Kharlamov
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* Email(s) : sasha_xarlamov@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module vgachargen
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import vgachargen_pkg::*;
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#(
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parameter int unsigned CLK_FACTOR_25M = 100 / 25,
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parameter CH_T_INIT_FILE_NAME = "lab_13_vga_ch_t.mem",
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parameter bit CH_T_INIT_FILE_IS_BIN = 1'b1,
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parameter CH_MAP_INIT_FILE_NAME = "lab_13_vga_ch_map.mem",
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parameter bit CH_MAP_INIT_FILE_IS_BIN = 1'b0,
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parameter COL_MAP_INIT_FILE_NAME = "lab_13_vga_col_map.mem",
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parameter bit COL_MAP_INIT_FILE_IS_BIN = 1'b0
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) (
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input logic clk_i, // системный синхроимпульс
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input logic clk100m_i, // клок с частотой 100МГц
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input logic rst_i, // сигнал сброса
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/*
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Интерфейс записи выводимого символа
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*/
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input logic char_map_req_i, // запрос к памяти выводимых символов
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input logic [ 9:0] char_map_addr_i, // адрес позиции выводимого символа
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input logic char_map_we_i, // сигнал разрешения записи кода
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input logic [ 3:0] char_map_be_i, // сигнал выбора байтов для записи
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input logic [31:0] char_map_wdata_i, // ascii-код выводимого символа
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output logic [31:0] char_map_rdata_o, // сигнал чтения кода символа
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/*
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Интерфейс установки цветовой схемы
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*/
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input logic col_map_req_i, // запрос к памяти цветов символов
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input logic [ 9:0] col_map_addr_i, // адрес позиции устанавливаемой схемы
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input logic col_map_we_i, // сигнал разрешения записи схемы
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input logic [ 3:0] col_map_be_i, // сигнал выбора байтов для записи
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input logic [31:0] col_map_wdata_i, // код устанавливаемой цветовой схемы
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output logic [31:0] col_map_rdata_o, // сигнал чтения кода схемы
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/*
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Интерфейс установки шрифта.
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*/
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input logic char_tiff_req_i, // запрос к памяти шрифтов символов
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input logic [ 9:0] char_tiff_addr_i, // адрес позиции устанавливаемого шрифта
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input logic char_tiff_we_i, // сигнал разрешения записи шрифта
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input logic [ 3:0] char_tiff_be_i, // сигнал выбора байтов для записи
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input logic [31:0] char_tiff_wdata_i, // отображаемые пиксели в текущей позиции шрифта
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output logic [31:0] char_tiff_rdata_o, // сигнал чтения пикселей шрифта
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output logic [3:0] vga_r_o, // красный канал vga
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output logic [3:0] vga_g_o, // зеленый канал vga
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output logic [3:0] vga_b_o, // синий канал vga
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output logic vga_hs_o, // линия горизонтальной синхронизации vga
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output logic vga_vs_o // линия вертикальной синхронизации vga
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);
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logic vga_clk_i;
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assign vga_clk_i = clk100m_i;
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if (CLK_FACTOR_25M == 0 || CLK_FACTOR_25M > 4) error_unsupported_factor error_unsupported_factor ();
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logic [3:0] char_map_be_gated;
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assign char_map_be_gated = char_map_be_i & {4{char_map_we_i & char_map_req_i}};
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logic [3:0] col_map_be_gated;
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assign col_map_be_gated = col_map_be_i & {4{col_map_we_i & col_map_req_i}};
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logic [3:0] char_tiff_be_gated;
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assign char_tiff_be_gated = char_tiff_be_i & {4{char_tiff_we_i & char_tiff_req_i}};
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logic arstn_i;
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assign arstn_i = ~rst_i;
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logic [VGA_MAX_H_WIDTH-1:0] hcount_pixels;
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logic [VGA_MAX_V_WIDTH-1:0] vcount_pixels;
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logic pixel_enable;
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logic pixel_enable_delayed;
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delay #(
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.DATA_WIDTH (1),
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.DELAY_BY (2)
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) pixel_enable_delay (
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (pixel_enable),
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.data_o (pixel_enable_delayed)
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);
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logic vga_vs_delayed;
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logic vga_vs;
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delay #(
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.DATA_WIDTH (1),
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.DELAY_BY (2)
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) vga_vs_delay (
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (vga_vs),
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.data_o (vga_vs_delayed)
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);
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logic vga_hs_delayed;
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logic vga_hs;
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delay #(
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.DATA_WIDTH (1),
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.DELAY_BY (2)
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) vga_hs_delay (
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (vga_hs),
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.data_o (vga_hs_delayed)
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);
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vga_block #(
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.CLK_FACTOR_25M (CLK_FACTOR_25M)
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) vga_block (
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.hcount_o (hcount_pixels),
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.vcount_o (vcount_pixels),
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.pixel_enable_o (pixel_enable),
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.vga_hs_o (vga_hs),
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.vga_vs_o (vga_vs)
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);
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logic [CH_MAP_ADDR_WIDTH-1:0] ch_map_addr_internal;
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logic [BITMAP_ADDR_WIDTH-1:0] bitmap_addr;
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logic [BITMAP_ADDR_WIDTH-1:0] bitmap_addr_delayed;
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delay #(
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.DATA_WIDTH (BITMAP_ADDR_WIDTH),
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.DELAY_BY (2)
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) bitmap_delay (
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (bitmap_addr),
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.data_o (bitmap_addr_delayed)
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);
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index_generator index_generator (
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.vcount_i (vcount_pixels),
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.hcount_i (hcount_pixels),
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.ch_map_addr_o (ch_map_addr_internal),
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.bitmap_addr_o (bitmap_addr)
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);
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logic [1:0] ch_map_byte_select;
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logic [1:0] ch_map_byte_select_delayed;
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assign ch_map_byte_select = ch_map_addr_internal[1:0];
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delay #(
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.DATA_WIDTH (2),
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.DELAY_BY (1)
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) ch_map_byte_select_delay (
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (ch_map_byte_select),
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.data_o (ch_map_byte_select_delayed)
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);
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logic [CH_T_ADDR_WIDTH-1:0] ch_t_addr_internal;
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logic [3:0][7:0] ch_map_data_word;
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assign ch_t_addr_internal = ch_map_data_word[ch_map_byte_select_delayed];
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true_dual_port_rw_bram #(
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.INIT_FILE_NAME (CH_MAP_INIT_FILE_NAME),
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.INIT_FILE_IS_BIN (CH_MAP_INIT_FILE_IS_BIN),
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.ADDR_WIDTH (10)
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) ch_map (
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.clka_i (clk_i),
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.clkb_i (vga_clk_i),
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.addra_i (char_map_addr_i),
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.addrb_i (ch_map_addr_internal[$left(ch_map_addr_internal):2]),
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.wea_i (char_map_be_gated),
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.dina_i (char_map_wdata_i),
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.douta_o (char_map_rdata_o),
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.doutb_o (ch_map_data_word)
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);
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logic [CH_T_DATA_WIDTH-1:0] ch_t_data_internal;
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logic [CH_T_ADDR_WIDTH-1:0] char_tiff_addr_128bit;
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assign char_tiff_addr_128bit = char_tiff_addr_i[$left(char_tiff_addr_i):2];
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logic [1:0] char_tiff_addr_offset_32bit;
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assign char_tiff_addr_offset_32bit = char_tiff_addr_i[1:0];
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logic [3:0][3:0] char_tiff_wea;
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always_comb begin : bin2onehot
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char_tiff_wea = '0;
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char_tiff_wea[char_tiff_addr_offset_32bit] = char_tiff_be_gated;
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end
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logic [6:0] char_tiff_addr_offset_128bit;
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logic [6:0] char_tiff_addr_offset_128bit_ff;
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assign char_tiff_addr_offset_128bit = {char_tiff_addr_offset_32bit, 5'b00000};
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logic [127:0] char_tiff_wdata_128bit;
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always_comb begin
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char_tiff_wdata_128bit = '0;
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char_tiff_wdata_128bit[char_tiff_addr_offset_128bit+:32] = char_tiff_wdata_i;
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end
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logic [127:0] char_tiff_rdata_128bit;
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assign char_tiff_rdata_o = char_tiff_rdata_128bit[char_tiff_addr_offset_128bit_ff+:32];
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always_ff @(posedge clk_i) begin
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char_tiff_addr_offset_128bit_ff <= char_tiff_addr_offset_128bit;
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end
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true_dual_port_rw_bram #(
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.INIT_FILE_NAME (CH_T_INIT_FILE_NAME),
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.INIT_FILE_IS_BIN (CH_T_INIT_FILE_IS_BIN),
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.NUM_COLS (16),
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.COL_WIDTH (8),
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.ADDR_WIDTH (CH_T_ADDR_WIDTH)
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) char_tiff (
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.clka_i (clk_i),
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.clkb_i (vga_clk_i),
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.addra_i (char_tiff_addr_128bit),
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.addrb_i (ch_t_addr_internal),
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.wea_i (char_tiff_wea),
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.dina_i (char_tiff_wdata_128bit),
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.douta_o (char_tiff_rdata_128bit),
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.doutb_o (ch_t_data_internal)
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);
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logic [7:0] col_map_data_internal;
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logic [7:0] col_map_data_internal_delayed;
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logic [3:0][7:0] col_map_data_internal_word;
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assign col_map_data_internal = col_map_data_internal_word[ch_map_byte_select_delayed];
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delay #(
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.DATA_WIDTH (8),
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.DELAY_BY (1)
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) col_map_data_delay (
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.clk_i (vga_clk_i),
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.arstn_i (arstn_i),
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.data_i (col_map_data_internal),
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.data_o (col_map_data_internal_delayed)
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);
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logic [3:0] fg_col_map_data;
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logic [3:0] bg_col_map_data;
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assign fg_col_map_data = col_map_data_internal_delayed[7:4];
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assign bg_col_map_data = col_map_data_internal_delayed[3:0];
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true_dual_port_rw_bram #(
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.INIT_FILE_NAME (COL_MAP_INIT_FILE_NAME),
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.INIT_FILE_IS_BIN (COL_MAP_INIT_FILE_IS_BIN),
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.ADDR_WIDTH (10)
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) col_map (
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.clka_i (clk_i),
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.clkb_i (vga_clk_i),
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.addra_i (col_map_addr_i),
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.addrb_i (ch_map_addr_internal[$left(ch_map_addr_internal):2]),
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.wea_i (col_map_be_gated),
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.dina_i (col_map_wdata_i),
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.douta_o (col_map_rdata_o),
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.doutb_o (col_map_data_internal_word)
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);
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logic currentPixel;
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assign currentPixel = ch_t_data_internal[bitmap_addr_delayed];
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logic [11:0] fg_color;
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assign fg_color = color_decode(fg_col_map_data);
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logic [11:0] bg_color;
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assign bg_color = color_decode(bg_col_map_data);
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// register outputs
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logic [3:0] vga_r_ff;
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logic [3:0] vga_r_next;
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logic [3:0] vga_g_ff;
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logic [3:0] vga_g_next;
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logic [3:0] vga_b_ff;
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logic [3:0] vga_b_next;
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logic vga_vs_ff;
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logic vga_vs_next;
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logic vga_hs_ff;
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logic vga_hs_next;
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assign vga_r_next = pixel_enable_delayed ? (currentPixel ? fg_color[11:8]: bg_color[11:8]) : '0;
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assign vga_g_next = pixel_enable_delayed ? (currentPixel ? fg_color[7:4] : bg_color[7:4]) : '0;
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assign vga_b_next = pixel_enable_delayed ? (currentPixel ? fg_color[3:0] : bg_color[3:0]) : '0;
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assign vga_vs_next = vga_vs_delayed;
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assign vga_hs_next = vga_hs_delayed;
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always_ff @(posedge vga_clk_i or negedge arstn_i) begin
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if (!arstn_i) begin
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vga_r_ff <= '0;
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vga_g_ff <= '0;
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vga_b_ff <= '0;
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vga_hs_ff <= '0;
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vga_vs_ff <= '0;
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end else begin
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vga_r_ff <= vga_r_next;
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vga_g_ff <= vga_g_next;
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vga_b_ff <= vga_b_next;
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vga_hs_ff <= vga_hs_next;
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vga_vs_ff <= vga_vs_next;
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end
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end
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assign vga_r_o = vga_r_ff;
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assign vga_g_o = vga_g_ff;
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assign vga_b_o = vga_b_ff;
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assign vga_hs_o = vga_hs_ff;
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assign vga_vs_o = vga_vs_ff;
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endmodule
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module clk_divider # (
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parameter int unsigned DIVISOR = 2
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) (
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input logic clk_i,
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input logic arstn_i,
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output logic strb_o
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);
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localparam int unsigned COUNTER_WIDTH = $clog2(DIVISOR);
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logic [COUNTER_WIDTH-1:0] counter_next;
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logic [COUNTER_WIDTH-1:0] counter_ff;
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assign counter_next = ~|counter_ff ? COUNTER_WIDTH'(DIVISOR - 1) : (counter_ff - COUNTER_WIDTH'(1));
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (~arstn_i) counter_ff <= '0;
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else counter_ff <= counter_next;
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end
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logic strb_ff;
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logic strb_next;
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assign strb_next = ~|counter_ff;
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (~arstn_i) strb_ff <= '0;
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else strb_ff <= strb_next;
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end
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assign strb_o = strb_ff;
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endmodule
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module delay #(
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parameter int unsigned DATA_WIDTH = 8,
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parameter int unsigned DELAY_BY = 2
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) (
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input logic clk_i,
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input logic arstn_i,
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input logic [DATA_WIDTH-1:0] data_i,
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output logic [DATA_WIDTH-1:0] data_o
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);
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logic [DELAY_BY-1:0][DATA_WIDTH-1:0] data_ff ;
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logic [DELAY_BY-1:0][DATA_WIDTH-1:0] data_next;
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if (DELAY_BY == 1) begin
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assign data_next = data_i;
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assign data_o = data_ff;
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end else begin
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assign data_next = {data_ff[DELAY_BY-2:0], data_i};
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assign data_o = data_ff[DELAY_BY-1];
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end
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) data_ff <= '0;
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else data_ff <= data_next;
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end
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endmodule
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module index_generator
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import vgachargen_pkg::*;
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(
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input logic [VGA_MAX_V_WIDTH -1:0] vcount_i,
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input logic [VGA_MAX_H_WIDTH -1:0] hcount_i,
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output logic [CH_MAP_ADDR_WIDTH-1:0] ch_map_addr_o,
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output logic [BITMAP_ADDR_WIDTH-1:0] bitmap_addr_o
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);
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logic [CH_H_WIDTH-1:0] haddr_chars;
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logic [CH_V_WIDTH-1:0] vaddr_chars;
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assign haddr_chars = CH_H_WIDTH'(hcount_i >> BITMAP_H_WIDTH);
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assign vaddr_chars = CH_V_WIDTH'(vcount_i >> BITMAP_V_WIDTH);
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`define _MULT_BY_80(_x) ((_x << 6) + (_x << 4))
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assign ch_map_addr_o = `_MULT_BY_80(vaddr_chars) + haddr_chars;
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`undef _MULT_BY_80
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logic [BITMAP_H_WIDTH-1:0] haddr_pixels;
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logic [BITMAP_V_WIDTH-1:0] vaddr_pixels;
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assign haddr_pixels = hcount_i[BITMAP_H_WIDTH-1:0];
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assign vaddr_pixels = vcount_i[BITMAP_V_WIDTH-1:0];
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`define _MULT_BY_8(_x) (_x << 3)
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assign bitmap_addr_o = `_MULT_BY_8(vaddr_pixels) + haddr_pixels;
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`undef _MULT_BY_8
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endmodule
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module timing_generator
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import vgachargen_pkg::*;
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(
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input logic clk_i,
|
||
input logic arstn_i,
|
||
input logic en_i,
|
||
|
||
output logic vga_hs_o,
|
||
output logic vga_vs_o,
|
||
|
||
// Display timing counters
|
||
output logic [VGA_MAX_H_WIDTH-1:0] hcount_o,
|
||
output logic [VGA_MAX_V_WIDTH-1:0] vcount_o,
|
||
output logic pixel_enable_o
|
||
|
||
);
|
||
|
||
logic [VGA_MAX_H_WIDTH-1:0] hcount_ff;
|
||
logic [VGA_MAX_H_WIDTH-1:0] hcount_next;
|
||
|
||
logic [VGA_MAX_V_WIDTH-1:0] vcount_ff;
|
||
logic vcount_en;
|
||
logic [VGA_MAX_V_WIDTH-1:0] vcount_next;
|
||
|
||
// Horizontal counter
|
||
assign hcount_next = ( hcount_ff < ( HTOTAL - 1 ) ) ? ( hcount_ff + 1 ) : ( '0 );
|
||
always_ff @ ( posedge clk_i or negedge arstn_i )
|
||
if ( ~arstn_i ) hcount_ff <= '0;
|
||
else if (en_i) hcount_ff <= hcount_next;
|
||
|
||
// Vertical counter
|
||
assign vcount_en = ( hcount_ff == ( HTOTAL - 1 ) ) & en_i;
|
||
assign vcount_next = ( vcount_ff < ( VTOTAL - 1 ) ) ? ( vcount_ff + 1 ) : ( '0 );
|
||
always_ff @( posedge clk_i or negedge arstn_i )
|
||
if ( ~arstn_i ) vcount_ff <= '0;
|
||
else if ( vcount_en ) vcount_ff <= vcount_next;
|
||
|
||
enum {
|
||
DISPLAY_S,
|
||
FRONT_S,
|
||
SYNC_S,
|
||
BACK_S
|
||
} hstate_ff, hstate_next,
|
||
vstate_ff, vstate_next;
|
||
|
||
always_ff @( posedge clk_i or negedge arstn_i )
|
||
if( ~arstn_i ) begin
|
||
hstate_ff <= DISPLAY_S;
|
||
vstate_ff <= DISPLAY_S;
|
||
end else if (en_i) begin
|
||
hstate_ff <= hstate_next;
|
||
vstate_ff <= vstate_next;
|
||
end
|
||
|
||
always_comb begin
|
||
hstate_next = hstate_ff;
|
||
unique case( hstate_ff)
|
||
DISPLAY_S: if( hcount_ff == HD - 1 ) hstate_next = FRONT_S;
|
||
|
||
FRONT_S: if( hcount_ff == HD + HF - 1 ) hstate_next = SYNC_S;
|
||
|
||
SYNC_S: if( hcount_ff == HD + HF + HR - 1 ) hstate_next = BACK_S;
|
||
|
||
BACK_S: if( hcount_ff == HTOTAL - 1 ) hstate_next = DISPLAY_S;
|
||
|
||
default: hstate_next = DISPLAY_S;
|
||
endcase
|
||
end
|
||
|
||
always_comb begin
|
||
vstate_next = vstate_ff;
|
||
if( vcount_en ) begin
|
||
unique case( vstate_ff)
|
||
DISPLAY_S: if( vcount_ff == VD - 1 ) vstate_next = FRONT_S;
|
||
|
||
FRONT_S: if( vcount_ff == VD + VF - 1 ) vstate_next = SYNC_S;
|
||
|
||
SYNC_S: if( vcount_ff == VD + VF + VR - 1 ) vstate_next = BACK_S;
|
||
|
||
BACK_S: if( vcount_ff == VTOTAL - 1 ) vstate_next = DISPLAY_S;
|
||
|
||
default: vstate_next = DISPLAY_S;
|
||
endcase
|
||
end
|
||
end
|
||
|
||
logic vga_vs_ff;
|
||
logic vga_vs_next;
|
||
|
||
assign vga_vs_next = vstate_next inside {DISPLAY_S, FRONT_S, BACK_S};
|
||
|
||
always_ff @(posedge clk_i or negedge arstn_i) begin
|
||
if (!arstn_i) vga_vs_ff <= 1'b1;
|
||
else if (en_i) vga_vs_ff <= vga_vs_next;
|
||
end
|
||
|
||
logic vga_hs_ff;
|
||
logic vga_hs_next;
|
||
|
||
assign vga_hs_next = hstate_next inside {DISPLAY_S, FRONT_S, BACK_S};
|
||
|
||
always_ff @(posedge clk_i or negedge arstn_i) begin
|
||
if (!arstn_i) vga_hs_ff <= 1'b1;
|
||
else if (en_i) vga_hs_ff <= vga_hs_next;
|
||
end
|
||
|
||
logic pixel_enable_ff;
|
||
logic pixel_enable_next;
|
||
|
||
assign pixel_enable_next = ( vstate_next == DISPLAY_S ) && ( hstate_next == DISPLAY_S );
|
||
|
||
always_ff @(posedge clk_i or negedge arstn_i) begin
|
||
if (!arstn_i) pixel_enable_ff <= 1'b0;
|
||
else if (en_i) pixel_enable_ff <= pixel_enable_next;
|
||
end
|
||
|
||
assign vga_hs_o = vga_hs_ff;
|
||
assign vga_vs_o = vga_vs_ff;
|
||
|
||
assign pixel_enable_o = pixel_enable_ff;
|
||
|
||
assign hcount_o = hcount_ff;
|
||
assign vcount_o = vcount_ff;
|
||
endmodule
|
||
|
||
module true_dual_port_rw_bram #(
|
||
parameter INIT_FILE_NAME = "",
|
||
parameter INIT_FILE_IS_BIN = 0,
|
||
parameter int unsigned COL_WIDTH = 8,
|
||
parameter int unsigned NUM_COLS = 4,
|
||
parameter int unsigned ADDR_WIDTH = 4,
|
||
localparam int unsigned DATA_WIDTH = NUM_COLS * COL_WIDTH,
|
||
localparam int unsigned DEPTH_WORDS = 2 ** ADDR_WIDTH
|
||
) (
|
||
input logic clka_i,
|
||
input logic clkb_i,
|
||
input logic [ADDR_WIDTH-1:0] addra_i,
|
||
input logic [ADDR_WIDTH-1:0] addrb_i,
|
||
input logic [NUM_COLS -1:0] wea_i,
|
||
input logic [DATA_WIDTH-1:0] dina_i,
|
||
output logic [DATA_WIDTH-1:0] douta_o,
|
||
output logic [DATA_WIDTH-1:0] doutb_o
|
||
);
|
||
logic [DATA_WIDTH-1:0] mem[DEPTH_WORDS];
|
||
|
||
if (INIT_FILE_NAME != "") begin : use_init_file
|
||
if (INIT_FILE_IS_BIN) initial $readmemb(INIT_FILE_NAME, mem, 0, DEPTH_WORDS-1);
|
||
else initial $readmemh(INIT_FILE_NAME, mem, 0, DEPTH_WORDS-1);
|
||
end else begin : init_bram_to_zero
|
||
initial begin
|
||
for (int unsigned i = 0; i < DEPTH_WORDS; ++i) mem[i] = '0;
|
||
end
|
||
end
|
||
|
||
always_ff @(posedge clka_i) begin
|
||
for (int i = 0; i < NUM_COLS; ++i) begin
|
||
if (wea_i[i]) mem[addra_i][i*COL_WIDTH+:COL_WIDTH] <= dina_i[i*COL_WIDTH+:COL_WIDTH];
|
||
end
|
||
end
|
||
|
||
always_ff @(posedge clka_i) begin
|
||
douta_o <= mem[addra_i];
|
||
end
|
||
|
||
always_ff @(posedge clkb_i) begin
|
||
doutb_o <= mem[addrb_i];
|
||
end
|
||
|
||
endmodule
|
||
|
||
module vga_block
|
||
import vgachargen_pkg::*;
|
||
#(
|
||
parameter int unsigned CLK_FACTOR_25M = 4
|
||
) (
|
||
input logic clk_i,
|
||
input logic arstn_i,
|
||
output logic [VGA_MAX_H_WIDTH-1:0] hcount_o,
|
||
output logic [VGA_MAX_V_WIDTH-1:0] vcount_o,
|
||
output logic pixel_enable_o,
|
||
output logic vga_hs_o,
|
||
output logic vga_vs_o
|
||
);
|
||
logic clk_divider_strb;
|
||
|
||
if (CLK_FACTOR_25M > 1) begin
|
||
clk_divider # (
|
||
.DIVISOR (CLK_FACTOR_25M)
|
||
) clk_divider (
|
||
.clk_i,
|
||
.arstn_i,
|
||
.strb_o (clk_divider_strb)
|
||
);
|
||
end else begin
|
||
assign clk_divider_strb = 1'b1;
|
||
end
|
||
|
||
timing_generator timing_generator (
|
||
.clk_i,
|
||
.arstn_i,
|
||
.en_i (clk_divider_strb),
|
||
.vga_hs_o,
|
||
.vga_vs_o,
|
||
.hcount_o,
|
||
.vcount_o,
|
||
.pixel_enable_o
|
||
|
||
);
|
||
endmodule
|