# RTL Analysis

**RTL** (**register transfer level**) is one of the abstraction levels in digital circuit design, where a circuit is described in terms of registers and the logic for data transfer between them.

Vivado provides RTL analysis tools, allowing you to detect and fix errors at an early stage, before running simulation or attempting to synthesize the project. To perform the analysis, you need to elaborate the project (`Open Elaborated Design`, see _fig. 1_).

![../.pic/Vivado%20Basics/06.%20RTL%20Analysis/fig_1.png](../.pic/Vivado%20Basics/06.%20RTL%20Analysis/fig_1.png)

_Figure 1. RTL analysis tools in the `Flow Navigator` window._

The result of elaboration is the display of a graphical schematic (described in more detail in the document "[Implementation Steps in FPGA](../Introduction/Implementation%20steps.md)"). If the schematic does not appear, click the `Schematic` button.

![../.pic/Vivado%20Basics/06.%20RTL%20Analysis/fig_2.png](../.pic/Vivado%20Basics/06.%20RTL%20Analysis/fig_2.png)

_Figure 2. Example of a schematic generated for the circuit described in the document "[Project Manager](./03.%20Project%20manager.md)"._

Suppose you found an error, modified the module code, and want to see the updated schematic. You click the `Schematic` button, a new tab opens, but the schematic has not changed. This is because opening a new schematic requires re-elaborating the project. To do this, either close the `Elaborated Design` window and reopen it, or click the `Reload Design` button at the top of the Vivado window, which appears in the informational message when the module code is updated (see _fig. 3_).

![../.pic/Vivado%20Basics/06.%20RTL%20Analysis/fig_3.png](../.pic/Vivado%20Basics/06.%20RTL%20Analysis/fig_3.png)

_Figure 3. Informational message indicating that the elaborated design is outdated due to source changes. The Reload button triggers re-elaboration for the updated code._

In addition to building the schematic, Vivado will analyze it, and any detected issues will be shown in the `Messages` tab at the bottom of the Vivado window (_fig. 4_).

![../.pic/Vivado%20Basics/06.%20RTL%20Analysis/fig_4.png](../.pic/Vivado%20Basics/06.%20RTL%20Analysis/fig_4.png)

_Figure 4. Messages window showing the results of completed operations. For display convenience, informational messages are hidden; only warnings are shown._

The problem with the messages window is that the number of messages accumulates quickly and becomes an overwhelming stream that is difficult to work with even with filters enabled. Moreover, messages persist between analysis runs — even if you fix an issue, the message about it will remain until you manually clear the messages window.

Starting from version 2023.1, Vivado includes a dedicated tool — a linter — that analyzes the code and reports issues in a separate window. Issues are grouped by type, and the list is cleared and regenerated every time the linter is run.

If you have already read the document "[Functional Bug Hunting Guide](./05.%20Bug%20hunting.md)", you may notice that the warnings Vivado displayed in the messages window are directly related to the errors we found during simulation. The difference is that Vivado reported these errors almost instantly, whereas we had to conduct a full investigation to find them. This is the power of this tool — it allows you to find most simple errors, freeing you to focus on more complex ones.

## Additional Resources

For more information on working with the schematic window, refer to the Vivado user guide: ["Vivado Design Suite User Guide: Using the Vivado IDE (UG893)"](https://docs.xilinx.com/r/en-US/ug893-vivado-ide) (section ["Using the Schematic Window"](https://docs.xilinx.com/r/en-US/ug893-vivado-ide/Using-the-Schematic-Window)).