# Lab Course

## Useful Resources

- [Creating a basic project with FPGA programming in Vivado](Vivado%20Basics/01.%20New%20project.md)
- [Basic Verilog Constructs](Basic%20Verilog%20structures/)
- [List of common errors in Vivado and SystemVerilog](Other/FAQ.md)
- [Testbench](Basic%20Verilog%20structures/Testbench.md)

## Lab Sequence by Group

### IB, ICT, CT, RT

1. Adder ([01. Adder](Labs/01.%20Adder))
2. ALU ([02. Arithmetic-logic unit](Labs/02.%20Arithmetic-logic%20unit))
3. Register file and external memory ([03. Register file and memory](Labs/03.%20Register%20file%20and%20memory))
4. Primitive programmable device ([04. Primitive programmable device](Labs/04.%20Primitive%20programmable%20device))

### PIN, PM

1. Adder ([01. Adder](Labs/01.%20Adder))
2. ALU ([02. Arithmetic-logic unit](Labs/02.%20Arithmetic-logic%20unit))
3. Register file and external memory ([03. Register file and memory](Labs/03.%20Register%20file%20and%20memory))
4. Primitive programmable device ([04. Primitive programmable device](Labs/04.%20Primitive%20programmable%20device))
5. Main decoder ([05. Main decoder](Labs/05.%20Main%20decoder))
6.
   1. Datapath ([07. Datapath](Labs/07.%20Datapath))
   2. Load-store unit integration ([09. LSU Integration](Labs/09.%20LSU%20Integration))
   3. Interrupt subsystem integration ([11. Interrupt Integration](Labs/11.%20Interrupt%20integration))
7. Peripheral units ([13. Peripheral units](Labs/13.%20Peripheral%20units))
8. Programming ([14. Programming](Labs/14.%20Programming))

### ICS

1. ALU ([02. Arithmetic-logic unit](Labs/02.%20Arithmetic-logic%20unit))
2.
   1. Memory ([03. Register file and memory](Labs/03.%20Register%20file%20and%20memory))
   2. Primitive programmable device ([04. Primitive programmable device](Labs/04.%20Primitive%20programmable%20device))
3. Main decoder ([05. Main decoder](Labs/05.%20Main%20decoder))
4. Datapath ([07. Datapath](Labs/07.%20Datapath))
5.
   1. Load-store unit ([08. Load-store unit](Labs/08.%20Load-store%20unit))
   2. Load-store unit integration ([09. LSU Integration](Labs/09.%20LSU%20Integration))
6.
   1. Interrupt controller ([10. Interrupt subsystem](Labs/10.%20Interrupt%20subsystem))
   2. Interrupt subsystem integration ([11. Interrupt Integration](Labs/11.%20Interrupt%20integration))
7. Peripheral units ([13. Peripheral units](Labs/13.%20Peripheral%20units))
8. Programming ([14. Programming](Labs/14.%20Programming))