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ЛР13. Изменение спецификации на контроллеры uart

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This commit is contained in:
Andrei Solodovnikov
2024-07-04 17:32:30 +03:00
parent 1f5c1bcebb
commit ffc6a564a5
3 changed files with 31 additions and 27 deletions
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2
Labs/13. Peripheral units/peripheral modules/uart_rx.sv
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@@ -25,7 +25,7 @@ module uart_rx (
output logic busy_o,
input logic [16:0] baudrate_i,
input logic parity_en_i,
input logic stopbit_i,
input logic [1:0] stopbit_i,
output logic [7:0] rx_data_o,
output logic rx_valid_o
//, input logic cfg_en_i,

4
Labs/13. Peripheral units/peripheral modules/uart_tx.sv
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@@ -25,7 +25,7 @@ module uart_tx (
output logic busy_o,
input logic [16:0] baudrate_i,
input logic parity_en_i,
input logic stopbit_i,
input logic [1:0] stopbit_i,
input logic [7:0] tx_data_i,
input logic tx_valid_i
//, input logic cfg_en_i,
@@ -161,7 +161,7 @@ module uart_tx (
baudgen_en = 1'b1;
if (bit_done)
begin
if (stopbit_i)
if (stopbit_i[1])
NS = STOP_BIT_LAST;
else
NS = IDLE;