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ЛР7. Исправление адресации в ext_mem

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Andrei Solodovnikov
2024-04-23 14:22:13 +03:00
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parent bcaea163e9
commit fedc917cab
1 changed files with 1 additions and 1 deletions
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Labs/Made-up modules/lab_07.ext_mem.sv
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@@ -34,7 +34,7 @@ assign ready_o = 1'b1;
logic [31:0] RAM [2**12]; logic [31:0] RAM [2**12];
logic [31:0] addr; logic [31:0] addr;
assign addr = addr_i >> 2; assign addr = addr_i;
always_ff@(posedge clk_i) begin always_ff@(posedge clk_i) begin
case(1) case(1)