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ЛР10. Исправление тб

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Добавление $sampled в сообщения об ошибках.
This commit is contained in:
Andrei Solodovnikov
2024-11-23 18:08:32 +03:00
parent c829845306
commit f101fb688a
2 changed files with 9 additions and 9 deletions
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12
Labs/10. Interrupt subsystem/lab_10.tb_csr.sv
View File

@@ -325,7 +325,7 @@ trap_mepc_a: assert property (
$rose(trap_i) |-> ##1 (mepc_o === pc_i) $rose(trap_i) |-> ##1 (mepc_o === pc_i)
)else begin )else begin
err_count++; err_count++;
$display("Incorrect mepc on trap : mepc_o = %08h while it should be %08h.\n", mepc_o, pc_i); $display("Incorrect mepc on trap : mepc_o = %08h while it should be %08h.\n", $sampled(mepc_o), $sampled(pc_i));
end end
@@ -334,7 +334,7 @@ trap_mcause_a: assert property (
($rose(trap_i) && (addr_i == MCAUSE_ADDR)) |-> ##1 (read_data_o === mcause_i) ($rose(trap_i) && (addr_i == MCAUSE_ADDR)) |-> ##1 (read_data_o === mcause_i)
)else begin )else begin
err_count++; err_count++;
$display("Incorrect mcause on trap : read_data_o = %08h while it should be %08h.\n", read_data_o, mcause_i); $display("Incorrect mcause on trap : read_data_o = %08h while it should be %08h.\n", $sampled(read_data_o), $sampled(mcause_i));
end end
string reg_name; string reg_name;
@@ -352,7 +352,7 @@ csr_read_a: assert property (
MCAUSE_ADDR : reg_name = "mcause "; MCAUSE_ADDR : reg_name = "mcause ";
default : reg_name = "ill_addr"; default : reg_name = "ill_addr";
endcase endcase
$display("Incorrect read from %s: read_data_o = %08h while it should be %08h.\n", reg_name, read_data_o, data_ref); $display("Incorrect read from %s: read_data_o = %08h while it should be %08h.\n", reg_name, $sampled(read_data_o), $sampled(data_ref));
end end
mie_a: assert property ( mie_a: assert property (
@@ -360,7 +360,7 @@ mie_a: assert property (
((addr_i === MIE_ADDR) && $rose(write_enable_i)) |=> (mie_o === data_ref) ((addr_i === MIE_ADDR) && $rose(write_enable_i)) |=> (mie_o === data_ref)
)else begin )else begin
err_count++; err_count++;
$display("Incorrect value of mie_o : mie_o = %08h while if should be %08h.\n", mie_o, data_ref); $display("Incorrect value of mie_o : mie_o = %08h while if should be %08h.\n", $sampled(mie_o), $sampled(data_ref));
end end
mepc_a: assert property ( mepc_a: assert property (
@@ -368,7 +368,7 @@ mepc_a: assert property (
((addr_i === MEPC_ADDR) && $rose(write_enable_i)) |=> (mepc_o === data_ref) ((addr_i === MEPC_ADDR) && $rose(write_enable_i)) |=> (mepc_o === data_ref)
)else begin )else begin
err_count++; err_count++;
$display("Incorrect value of mepc_o : mepc_o = %08h while if should be %08h.\n", mepc_o, data_ref); $display("Incorrect value of mepc_o : mepc_o = %08h while if should be %08h.\n", $sampled(mepc_o), $sampled(data_ref));
end end
mtvec_a: assert property ( mtvec_a: assert property (
@@ -376,7 +376,7 @@ mtvec_a: assert property (
((addr_i === MTVEC_ADDR) && $rose(write_enable_i)) |=> (mtvec_o === data_ref) ((addr_i === MTVEC_ADDR) && $rose(write_enable_i)) |=> (mtvec_o === data_ref)
)else begin )else begin
err_count++; err_count++;
$display("Incorrect value of mtvec_o : mtvec_o = %08h while if should be %08h.\n", mtvec_o, data_ref); $display("Incorrect value of mtvec_o : mtvec_o = %08h while if should be %08h.\n", $sampled(mtvec_o), $sampled(data_ref));
end end
mepc_stability_a: assert property ( mepc_stability_a: assert property (

6
Labs/10. Interrupt subsystem/lab_10.tb_irq.sv
View File

@@ -383,9 +383,9 @@ endtask
//logic irq, irq_ret; //logic irq, irq_ret;
task eror_info(irq, irq_ret); task eror_info(irq, irq_ret);
if (irq_o!=irq) begin $error("invalid irq_o = %b, expected value %b." , irq_o, irq ); err_count++; end if (irq_o!=irq) begin $error("invalid irq_o = %b, expected value %b." , $sampled(irq_o ), irq )); err_count++; end
if (irq_ret_o!=irq_ret) begin $error("invalid irq_ret_o = %b, expected value %b." , irq_ret_o, irq_ret); err_count++; end if (irq_ret_o!=irq_ret) begin $error("invalid irq_ret_o = %b, expected value %b." , $sampled(irq_ret_o), irq_ret)); err_count++; end
if (irq_cause_o!=32'h8000_0010) begin $error("invalid irq_cause_o = %h, expected value 32'h8000_0010.", irq_cause_o ); err_count++; end if (irq_cause_o!=32'h8000_0010) begin $error("invalid irq_cause_o = %h, expected value 32'h8000_0010.", $sampled(irq_cause_o) ); err_count++; end
endtask endtask
endmodule endmodule