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Обновление тестбенчей

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This commit is contained in:
Andrei Solodovnikov
2024-09-09 12:01:27 +03:00
parent ecd342b022
commit e9665941f9
14 changed files with 302 additions and 343 deletions
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Labs/Made-up modules/lab_03.register_file.sv
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@@ -8,7 +8,7 @@
See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
module rf_riscv(
module register_file(
input logic clk_i,
input logic write_enable_i,