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Обновление тестбенчей

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This commit is contained in:
Andrei Solodovnikov
2024-09-09 12:01:27 +03:00
parent ecd342b022
commit e9665941f9
14 changed files with 302 additions and 343 deletions
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30
Labs/Made-up modules/lab_02.alu.sv
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@@ -1,6 +1,6 @@
/* -----------------------------------------------------------------------------
* Project Name : Architectures of Processor Systems (APS) lab work
* File : alu_riscv.sv
* File : alu.sv
* Organization : National Research University of Electronic Technology (MIET)
* Department : Institute of Microdevices and Control Systems
* Author(s) : Alexey Kozin
@@ -10,22 +10,22 @@ See LICENSE file for licensing details.
* ------------------------------------------------------------------------------
*/
parameter ALUOP_W = 5;
parameter OP_W = 32;
parameter SHIFT_W = $clog2(OP_W);
parameter STAGE_LEN = OP_W+1;
parameter HASH_LEN = 1000;
parameter START_CODING = 10366;
parameter START_MUX = START_CODING+100;
module alu_riscv (
input logic [ALUOP_W-1:0] alu_op_i,
input logic [OP_W-1:0] a_i,
input logic [OP_W-1:0] b_i,
output logic [OP_W-1:0] result_o,
output logic flag_o
module alu (
input logic [4:0] alu_op_i,
input logic [31:0] a_i,
input logic [31:0] b_i,
output logic [31:0] result_o,
output logic flag_o
);
localparam ALUOP_W = 5;
localparam OP_W = 32;
localparam SHIFT_W = $clog2(OP_W);
localparam STAGE_LEN = OP_W+1;
localparam HASH_LEN = 1000;
localparam START_CODING = 10366;
localparam START_MUX = START_CODING+100;
genvar i, j, k;
logic [OP_W-1:0] skjfbsbgisg [0:STAGE_LEN-1];