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Обновление тестбенчей

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This commit is contained in:
Andrei Solodovnikov
2024-09-09 12:01:27 +03:00
parent ecd342b022
commit e9665941f9
14 changed files with 302 additions and 343 deletions
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21
Labs/07. Datapath/lab_07.tb_processor_system.sv
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@@ -18,17 +18,20 @@ module lab_07_tb_processor_system();
.rst_i(rst)
);
initial clk = 0;
initial clk = 0;
always #10 clk = ~clk;
initial begin
$display( "\nTest has been started.");
rst = 1;
#40;
rst = 0;
#800;
$display("\n The test is over \n See the internal signals of the module on the waveform \n");
$finish;
end
$display( "\nTest has been started.");
rst = 1;
#40;
rst = 0;
#800;
$display("\n The test is over \n See the internal signals of the module on the waveform \n");
$finish;
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.")
$fatal();
end
stall_seq: assert property (
@(posedge system.core.clk_i) disable iff ( system.core.rst_i )