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Обновление тестбенчей

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This commit is contained in:
Andrei Solodovnikov
2024-09-09 12:01:27 +03:00
parent ecd342b022
commit e9665941f9
14 changed files with 302 additions and 343 deletions
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13
Labs/06. Main memory/lab_06.tb_data_mem.sv
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@@ -30,8 +30,6 @@ module lab_06_tb_data_mem;
int err_cnt = 0;
static bit simulation_finished;
data_mem DUT (.*);
task read_request(input logic [31:0] address, output logic [31:0] data);
@@ -173,8 +171,10 @@ module lab_06_tb_data_mem;
random_test();
$display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
simulation_finished = 1;
$finish;
#5;
$display("You're trying to run simulation that has finished. Aborting simulation.")
$fatal();
end
logic [31:0] ram_data;
@@ -275,13 +275,6 @@ module lab_06_tb_data_mem;
$display("Error at %t. ram[%d][31:24] is unstable without write request", $time(), $sampled(addr_reg));
end
always @(posedge clk_i) begin
if(simulation_finished) begin
$finish;
end
end
always @(posedge clk_i) begin
if (err_cnt >= 10) begin
$display("\nTest has been stopped after 10 errors"); $stop();