Обновление тестбенчей

Labs/02. Arithmetic-logic unit/lab_02.tb_alu.sv

@@ -63,6 +63,9 @@ initial
     direct_test();
     $display("\nTest has been finished\nNumber of errors: %d\n", err_cnt);
     $finish();
+    #5;
+    $display("You're trying to run simulation that has finished. Aborting simulation.")
+    $fatal();
   end
 
 task X_test();
@@ -247,23 +250,22 @@ end
 
 endmodule
 
-parameter ALUOP_W = 5;
-parameter OP_W = 32;
-parameter SHIFT_W = $clog2(OP_W);
-parameter STAGE_LEN = OP_W+1;
-parameter HASH_LEN = 1000;
-parameter START_CODING = 10366;
-parameter START_MUX = START_CODING+100;
 
 module alu_ref (
-    input  logic [ALUOP_W-1:0] alu_op_i,
-    input  logic [OP_W-1:0]    a_i,
-    input  logic [OP_W-1:0]    b_i,
-    output logic [OP_W-1:0]    result_o,
-    output logic               flag_o
+    input  logic [ 4:0] alu_op_i,
+    input  logic [31:0] a_i,
+    input  logic [31:0] b_i,
+    output logic [31:0] result_o,
+    output logic        flag_o
 );
 
-
+localparam ALUOP_W = 5;
+localparam OP_W = 32;
+localparam SHIFT_W = $clog2(OP_W);
+localparam STAGE_LEN = OP_W+1;
+localparam HASH_LEN = 1000;
+localparam START_CODING = 10366;
+localparam START_MUX = START_CODING+100;
 
 genvar i, j, k;