diff --git a/Labs/01. Adder/tb_fulladder.sv b/Labs/01. Adder/tb_fulladder.sv
index 816d70b..2150799 100644
--- a/Labs/01. Adder/tb_fulladder.sv	
+++ b/Labs/01. Adder/tb_fulladder.sv	
@@ -28,27 +28,31 @@ parameter TEST_VALUES = 8;
         .carry_o(tb_carry_o)
     );
 
-    integer     i;
+    integer     i, err_count = 0;
     reg [4:0] running_line;
     reg [5*8-1:0] line_dump;
+    wire sum_dump;
+    wire carry_o_dump;
 
     assign tb_a_i = running_line[4];
     assign tb_b_i = running_line[3];
     assign tb_carry_i = running_line[2];
+    assign sum_dump = running_line[1];
+    assign carry_o_dump = running_line[0];
 
     initial begin
-        $display("START simulation of 1-bit fulladder.");
-        $display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
-        for (i = 0; i < TEST_VALUES; i = i + 1) begin
-            running_line = line_dump[i*5+:5];
-            #TIME_OPERATION;
-        end
-        $display("FINISH simulation");
-        $display(
-            "Now you should open the waveform window",
-            "and visually prove correctness of the design"
-        );
-
+        $display( "Start test: ");
+        for ( i = 0; i < TEST_VALUES; i = i + 1 )
+            begin
+                running_line = line_dump[i*5+:5];
+                #TIME_OPERATION;
+                if( (tb_carry_o !== carry_o_dump) || (tb_sum_o !== sum_dump) ) begin
+                    $display("ERROR! carry_i = %b; (a)%b + (b)%b = ", tb_carry_i, tb_a_i, tb_b_i, "(carry_o)%b (sum_o)%b;", tb_carry_o, tb_sum_o, " carry_o_dump: %b, sum_dump: %b", carry_o_dump, sum_dump);
+                    err_count = err_count + 1'b1;
+                end
+            end
+        $display("Number of errors: %d", err_count);
+        if( !err_count )  $display("\nfulladder SUCCESS!!!\n");
         $finish();
     end
 
diff --git a/Labs/01. Adder/tb_fulladder4.sv b/Labs/01. Adder/tb_fulladder4.sv
index 182c6ee..4c5a9ca 100644
--- a/Labs/01. Adder/tb_fulladder4.sv	
+++ b/Labs/01. Adder/tb_fulladder4.sv	
@@ -39,20 +39,32 @@ module tb_fulladder4();
     assign sum_dump = running_line[4:1];
     assign carry_o_dump = running_line[0];
 
+`ifdef __debug__
+    initial begin
+        $display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
+        for ( i = 0; i < TEST_VALUES; i = i + 1 )
+            begin
+                running_line = line_dump[i*14+:14];
+                #TIME_OPERATION;
+                 if( (tb_carry_o !== carry_o_dump) || (tb_sum_o !== sum_dump) ) begin
+                    $display("ERROR! carry_i = %b; (a)%h + (b)%h = ", tb_carry_i, tb_a_i, tb_b_i, "(carry_o)%b (sum_o)%h;", tb_carry_o, tb_sum_o, " carry_o_dump: %b, sum_dump: %h", carry_o_dump, sum_dump);
+                    err_count = err_count + 1'b1;
+                end
+            end
+        $display("Number of errors: %d", err_count);
+        if( !err_count )  $display("\nfulladder4 SUCCESS!!!\n");
+        $finish();
+    end
+`else
     initial begin
-        $display("START simulation of 4-bit fulladder.");
-        $display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
         for ( i = TEST_VALUES-1; i >=0 ; i = i - 1 )
             begin
                 running_line = line_dump[i*14+:14];
                 #TIME_OPERATION;
             end
-        $display("FINISH simulation");
-        $display(
-            "Now you should open the waveform window",
-            "and visually prove correctness of the design"
-        );
+        $finish();
     end
+`endif
 
     initial line_dump = {
     14'h1787,
@@ -456,4 +468,4 @@ module tb_fulladder4();
     14'h108c,
     14'h1512};
 
-endmodule
+endmodule
\ No newline at end of file