From d8f51ccf655cd7ab73025ed1c2dbb750e89ed491 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <voultboy@yandex.ru>
Date: Fri, 15 Sep 2023 15:22:56 +0300
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---
 Labs/01. Adder/tb_fulladder.sv                   | 4 ++--
 Labs/01. Adder/tb_fulladder32.sv                 | 4 ++--
 Labs/01. Adder/tb_fulladder4.sv                  | 4 ++--
 Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv | 4 ++--
 4 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/Labs/01. Adder/tb_fulladder.sv b/Labs/01. Adder/tb_fulladder.sv
index a8abf92..66d135e 100644
--- a/Labs/01. Adder/tb_fulladder.sv	
+++ b/Labs/01. Adder/tb_fulladder.sv	
@@ -41,7 +41,7 @@ parameter TEST_VALUES = 8;
 
     integer     i, err_count = 0;
     reg [4:0] running_line;
-
+    reg [5*8-1:0] line_dump;
     wire sum_dump;
     wire carry_o_dump;
 
@@ -67,7 +67,7 @@ parameter TEST_VALUES = 8;
         $finish();
     end
 
-    reg [5*8-1:0] line_dump = {
+    initial line_dump = {
     5'b00000,
     5'b10010,
     5'b01010,
diff --git a/Labs/01. Adder/tb_fulladder32.sv b/Labs/01. Adder/tb_fulladder32.sv
index 9cb1693..d2b597f 100644
--- a/Labs/01. Adder/tb_fulladder32.sv	
+++ b/Labs/01. Adder/tb_fulladder32.sv	
@@ -40,7 +40,7 @@ parameter TEST_VALUES = 3000;
 
     integer     i, err_count = 0;
     reg [97:0] running_line;
-    
+    reg [98*3000:0] line_dump;
     wire [31:0] sum_dump;
     wire        carry_o_dump;
 
@@ -76,7 +76,7 @@ parameter TEST_VALUES = 3000;
         $finish();
     end
 `endif
-reg [98*3000:0] line_dump = {
+initial line_dump = {
 98'h04854d49302257a06d29e93a6,
 98'h2c7c1598c1ae5ec36b8a9d171,
 98'h2cb0a119624dd484b3bf9d678,
diff --git a/Labs/01. Adder/tb_fulladder4.sv b/Labs/01. Adder/tb_fulladder4.sv
index f0bb6f1..f3b7f0d 100644
--- a/Labs/01. Adder/tb_fulladder4.sv	
+++ b/Labs/01. Adder/tb_fulladder4.sv	
@@ -40,7 +40,7 @@ module tb_fulladder4();
 
     integer     i, err_count = 0;
     reg [13:0] running_line;
-
+    reg [14*400:0] line_dump;
     wire [3:0] sum_dump;
     wire       carry_o_dump;
 
@@ -77,7 +77,7 @@ module tb_fulladder4();
     end
 `endif
 
-    reg [14*400:0] line_dump = {
+    initial line_dump = {
     14'h1787,
     14'h1787,
     14'h1f8b,
diff --git a/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv b/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv
index 2341738..e7369f9 100644
--- a/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv	
+++ b/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv	
@@ -46,7 +46,7 @@ alu_riscv DUT
 
 integer     i, err_count = 0;
 reg [8*9:1] operator_type;
-
+reg [103*10000:0] line_dump;
 wire [31:0] result_dump;
 wire        comparison_result_dump;
 
@@ -98,7 +98,7 @@ always @(*) begin
  endcase
 end
 
-reg [103*10000:0] line_dump = {
+initial line_dump = {
 103'h1e88592d984c690cac00000000,
 103'h18f51e266e7dff015e00000000,
 103'h22fd89520d06582ef800000000,