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ЛР3. Исправление подключения рф в nexys-модуле

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В модуле использовался старый прототип подключения регистрового
файла.

Closes #13.
This commit is contained in:
Andrei Solodovnikov
2023-10-09 13:21:05 +03:00
parent d0441fd84f
commit d3058e182a
1 changed files with 8 additions and 9 deletions
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17
Labs/03. Register file and memory/board files/nexys_rf_riscv.sv
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@@ -31,15 +31,14 @@ reg [31:0] rd2;
rf_riscv DUT rf_riscv DUT
( (
.clk (CLK100), .clk_i (CLK100 ),
.A1 (a1), .write_addr_i (a1 ),
.A2 (a2), .read_addr1_i (a2 ),
.A3 (a3), .read_addr2_i (a3 ),
.WD3 (WD3), .write_data_i (WD3 ),
.WE (WE), .write_enable_i (WE ),
.read_data1_o (RD1 ),
.RD1 (RD1), .read_data2_o (RD2 )
.RD2 (RD2)
); );
assign LED = {1'b0, a1, a2, a3}; assign LED = {1'b0, a1, a2, a3};