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Вынос информации о защелках в отдельный документ

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Andrei Solodovnikov
2024-02-03 12:15:17 +03:00
parent af6ef85074
commit d215a215b8
5 changed files with 82 additions and 78 deletions
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.github/SUMMARY.md vendored
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@@ -41,6 +41,7 @@
- [Мультиплексоры](Basic%20Verilog%20structures/Multiplexors.md)
- [Регистры](Basic%20Verilog%20structures/Registers.md)
- [Конкатенация](Basic%20Verilog%20structures/Concatenation.md)
- [Защелки](Basic%20Verilog%20structures/Latches.md)
- [О различиях между блокирующими и неблокирующими присваиваниями](Basic%20Verilog%20structures/Assignments.md)
- [Контроллеры](Basic%20Verilog%20structures/Controllers.md)
- [Тестовое окружение](Basic%20Verilog%20structures/Testbench.md)