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ЛР1. Исправление подписи к листингу 2

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Andrei Solodovnikov
2024-09-18 17:27:25 +03:00
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Labs/01. Adder/README.md
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@@ -171,7 +171,7 @@ module testbench(); // <- Не имеет ни входов, ни
endmodule endmodule
``` ```
_Листинг 2. SystemVerilog-код тестбенча для модуля example._ _Листинг 2. SystemVerilog-код тестбенча для модуля half_adder._
![../../.pic/Labs/lab_01_adder/fig_04.png](../../.pic/Labs/lab_01_adder/fig_04.png) ![../../.pic/Labs/lab_01_adder/fig_04.png](../../.pic/Labs/lab_01_adder/fig_04.png)