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ЛР8. Добавление endmodule в lab_08.lsu.sv

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Andrei Solodovnikov
2023-11-28 10:32:43 +03:00
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parent 9aa5fcdc7a
commit c21defe65c
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Labs/Made-up modules/lab_08.lsu.sv
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@@ -118,3 +118,5 @@ always_comb begin
default:mem_wd_o <= 32'd0; default:mem_wd_o <= 32'd0;
endcase endcase
end end
endmodule