diff --git a/.pic/Labs/lab_15_programming_device/fig_04.drawio.svg b/.pic/Labs/lab_15_programming_device/fig_04.drawio.svg index 97852ae..7f13a8a 100644 --- a/.pic/Labs/lab_15_programming_device/fig_04.drawio.svg +++ b/.pic/Labs/lab_15_programming_device/fig_04.drawio.svg @@ -1,4 +1,4 @@ -
clk_i

rst_i

входные сигналы
255
req
внутренний сигнал, оборванный для улучшения читаемости схемы
LOAD/
STORE
UNIT
Core

rst_i
mem_rd_i
clk_i
Instruction
Memory
RA
RD
instr_i
mem_size_o
instr_addr
instr
mem_we_o
mem_req_o
mem_wd_o
mem_addr_o
instr_addr_o
3
stall_i
32
32
core_req_i
core_we_i
core_size_i
core_wd_i
core_addr_i
core_stall_o
core_rd_o
mem_wd_o
32
mem_be_o
mem_we_o
mem_req_o
mem_ready_i
clk_i
mem_addr_o
mem_rd_i
32
Data
Memory
A
WE
RD
clk_i
req
WD
BE

8
/

out [0]
req
[31:24]
{8'd0,[23:0]}
Periph
Device
1
A
WE
RD
clk_i
req
WD
out [1]
req
Periph
Device
255
A
WE
RD
clk_i
req
WD
out [255]
req
OneHot Encoder
in
out

256
/

0
1
32
32
32
32
1'b1
rst_i

rst_i

rst_i

rst_i

rst_i

rst_i

Bluster
clk_i
rst_i

rst_i

instr_wdata_o
instr_addr_o
instr_we_o
data_wdata_o
data_addr_o
data_we_o
tx_o
WE
WA
WD
32
32
32
32
core_reset_o
4
32
32
req
1
0
1
0
1
0
1
0
1
0
4'hf
tx_o
rx_i

rx_i

tx_o
выходной сигнал
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rst_i

rst_i
clk_i
clk_i

rst_i

rst_i
входные сигналы
входные сигналы
255
255
req
req
внутренний сигнал, оборванный для улучшения читаемости схемы
внутренний сигнал, оборванный для улучшения читаемости схемы
LOAD/
STORE
UNIT
LOAD/...
Core

Core...
rst_i
rst...
mem_rd_i
mem_rd_i
clk_i
clk_i
Instruction
Memory
Instruction...
RA
RA
RD
RD
instr_i
instr_i
mem_size_o
mem_size_o
instr_addr
instr_addr
instr
instr
mem_we_o
mem_we_o
mem_req_o
mem_req_o
mem_wd_o
mem_wd_o
mem_addr_o
mem_addr_o
instr_addr_o
instr_addr_o
3
3
stall_i
stall...
32
32
32
32
core_req_i
core_req_i
core_we_i
core_we_i
core_size_i
core_size_i
core_wd_i
core_wd_i
core_addr_i
core_addr_i
core_stall_o
core_stall_o
core_rd_o
core_rd_o
mem_wd_o
mem_wd_o
32
32
mem_be_o
mem_be_o
mem_we_o
mem_we_o
mem_req_o
mem_req_o
mem_ready_i
mem_ready_i
clk_i
clk_i
mem_addr_o
mem_addr_o
mem_rd_i
mem_rd_i
32
32
Data
Memory
Data...
A
A
WE
WE
RD
RD
clk_i
clk_i
req
req
WD
WD
BE
BE

8
/

8...
out [0]
out [0]
req
req
[31:24]
[31:24]
{8'd0,[23:0]}
{8'd0,[23:0...
Periph
Device
1
Periph...
A
A
WE
WE
RD
RD
clk_i
clk_i
req
req
WD
WD
out [1]
out [1]
req
req
Periph
Device
255
Periph...
A
A
WE
WE
RD
RD
clk_i
clk_i
req
req
WD
WD
out [255]
out [255]
req
req
OneHot Encoder
OneHot Encoder
in
in
out
out

256
/

256...
0
0
1
1
32
32
32
32
32
32
32
32
1'b1
1'b1
rst_i
rst...
rst_i
rst...

rst_i

rst_i
rst_i
rst...

rst_i

rst_i
Bluster
Bluster
clk_i
clk_i
rst_i
rst...

rst_i

rst_i
instr_wdata_o
instr_wdata...
instr_addr_o
instr_addr_o
instr_we_o
instr_we_o
data_wdata_o
data_wdata_o
data_addr_o
data_addr_o
data_we_o
data_we_o
tx_o
tx_o
WE
WE
WA
WA
WD
WD
32
32
32
32
32
32
32
32
core_reset_o
core_reset_o
4
4
32
32
32
32
req
req
1
0
1...
1
0
1...
1
0
1...
1
0
1...
1
0
1...
4'hf
4'hf
tx_o
tx_o
rx_i
rx_i

rx_i

rx_i
tx_o
tx_o
выходной сигнал
выходной сигнал
Text is not SVG - cannot display
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