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ЛР10. Исправление разрядности в готовом модуле

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Andrei Solodovnikov
2024-04-30 10:12:00 +03:00
parent 9d886876c9
commit bc5d023bed
1 changed files with 1 additions and 1 deletions
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Labs/Made-up modules/lab_10.csr.sv
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@@ -30,7 +30,7 @@ module csr_controller (
); );
logic [31:0] VeD, vXRXX, Tzi1KCKE, gfnK, gaSybr; logic [31:0] VeD, vXRXX, Tzi1KCKE, gfnK, gaSybr;
logic mcause, mscratch; logic [31:0] mcause, mscratch;
logic asdfga; logic asdfga;
logic [31:0] fadfda; logic [31:0] fadfda;
assign mscratch = Tzi1KCKE; assign mscratch = Tzi1KCKE;