From b14bcf3ed6831ce3fa3516f8a16e32e6c5fa3a08 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 8 May 2024 19:59:48 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9B=D0=A07.=20=D0=98=D1=81=D0=BF=D1=80=D0=B0?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=B3=D0=BE=D1=82=D0=BE?= =?UTF-8?q?=D0=B2=D0=BE=D0=B3=D0=BE=20=D0=BC=D0=BE=D0=B4=D1=83=D0=BB=D1=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/Made-up modules/lab_07.ext_mem.sv | 106 ++++++++++++++++--------- 1 file changed, 70 insertions(+), 36 deletions(-) diff --git a/Labs/Made-up modules/lab_07.ext_mem.sv b/Labs/Made-up modules/lab_07.ext_mem.sv index f7f16e7..3a8ebd3 100644 --- a/Labs/Made-up modules/lab_07.ext_mem.sv +++ b/Labs/Made-up modules/lab_07.ext_mem.sv @@ -8,6 +8,7 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. * ------------------------------------------------------------------------------ */ + module ext_mem( input logic clk_i, input logic mem_req_i, @@ -18,49 +19,82 @@ module ext_mem( output logic [31:0] read_data_o, output logic ready_o ); - - -`define akjsdnnaskjdndat $clog2(128) -`define cdyfguvhbjnmkdat $clog2(`akjsdnnaskjdndat) -`define qwenklfsaklasddat $clog2(`cdyfguvhbjnmkdat) -`define asdasdhkjasdsadat (34>>`cdyfguvhbjnmkdat) - -logic [31:0] read_data; -logic [3:0] be; -assign be = byte_enable_i; assign ready_o = 1'b1; +parameter DATA_MEM_SIZE_WORDS = 4096; +logic [31:0] ram [DATA_MEM_SIZE_WORDS]; - -logic [31:0] RAM [2**12]; - -logic [31:0] addr; -assign addr = addr_i; - -always_ff@(posedge clk_i) begin +always_ff @(posedge clk_i) begin case(1) - !mem_req_i||write_enable_i: read_data_o <= read_data_o; - default: begin - read_data_o['h1f:'h1c]<=RAM[addr[13'o10+13'b101:'hBA & 'h47]][{5{1'b1}}:{3'd7,2'b00}]; - read_data_o[42-23-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h47]][19:{1'b1,4'h0}]; - read_data_o[`akjsdnnaskjdndat-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h47]][{3{1'b1}}:{1'b1,2'h0}]; - read_data_o[42-19-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h47]][23:{{2{2'b10}},1'b0}]; - read_data_o['h1b:'h18]<=RAM[addr[13'o10+13'b101:'hBA & 'h47]][27:{2'b11,3'b000}]; - read_data_o[`akjsdnnaskjdndat+`asdasdhkjasdsadat:(`akjsdnnaskjdndat+`asdasdhkjasdsadat)-`cdyfguvhbjnmkdat]<=RAM[addr[13'o10+13'b101:'hBA & 'h47]][11:8]; - read_data_o[`akjsdnnaskjdndat-`asdasdhkjasdsadat-:`asdasdhkjasdsadat]<=RAM[addr[13'o10+13'b101:'hBA & 'h47]][3:0]; - read_data_o[(`akjsdnnaskjdndat<<(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat))+(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat):12]<=RAM[addr[13'o10+13'b101:'hBA & 'h47]][{4{1'b1}}:12]; - end + !mem_req_i||write_enable_i: read_data_o <= read_data_o; + default: read_data_o <= ram[addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]]; endcase end always_ff @(posedge clk_i) begin - if(write_enable_i&mem_req_i&be[4'o14>>2]) RAM[addr[13'o10+13'b101:'hBA & 'h47]][{5{1'b1}}:{3'd7,2'b00}] <= write_data_i['h1f:'h1c]; - if(write_enable_i&mem_req_i&be[7'd5>>1]) RAM[addr[13'o10+13'b101:'hBA & 'h47]][19:{1'b1,4'h0}] <= write_data_i[42-23-:`asdasdhkjasdsadat]; - if(write_enable_i&mem_req_i&be[16'haaaa&16'h5555]) RAM[addr[13'o10+13'b101:'hBA & 'h47]][{3{1'b1}}:{1'b1,2'h0}] <= write_data_i[`akjsdnnaskjdndat-:`asdasdhkjasdsadat]; - if(write_enable_i&mem_req_i&be[7'd2-$clog2(1)]) RAM[addr[13'o10+13'b101:'hBA & 'h47]][23:{{2{2'b10}},1'b0}] <= write_data_i[42-19-:`asdasdhkjasdsadat]; - if(write_enable_i&mem_req_i&be[4'o17&(4'o14>>2)]) RAM[addr[13'o10+13'b101:'hBA & 'h47]][27:{2'b11,3'b000}] <= write_data_i['h1b:'h18]; - if(write_enable_i&mem_req_i&be[3'sb111>>8]) RAM[addr[13'o10+13'b101:'hBA & 'h47]][11:{1'b1,{3{1'b0}}}] <= write_data_i[`akjsdnnaskjdndat+`asdasdhkjasdsadat:(`akjsdnnaskjdndat+`asdasdhkjasdsadat)-`cdyfguvhbjnmkdat]; - if(write_enable_i&mem_req_i&be[$clog2(1)]) RAM[addr[13'o10+13'b101:'hBA & 'h47]][{2{1'b1}}:{3{1'b0}}] <= write_data_i[`akjsdnnaskjdndat-`asdasdhkjasdsadat-:`asdasdhkjasdsadat]; - if(write_enable_i&mem_req_i&be[4'o13&4'o25]) RAM[addr[13'o10+13'b101:'hBA & 'h47]][{4{1'b1}}:4'b1100] <= write_data_i[(`akjsdnnaskjdndat<<(`asdasdhkjasdsadat-`cdyfguvhbjnmkdat)) + (`asdasdhkjasdsadat-`cdyfguvhbjnmkdat):12]; + case({mem_req_i, write_enable_i, byte_enable_i}) + 6'd49: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [7:0] <= write_data_i[7:0]; + end + 6'd50: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [15:8] <= write_data_i[15:8]; + end + 6'd51: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [7:0] <= write_data_i[7:0]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [15:8] <= write_data_i[15:8]; + end + 6'd52: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [23:16] <= write_data_i[23:16]; + end + 6'd53: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [7:0] <= write_data_i[7:0]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [23:16] <= write_data_i[23:16]; + end + 6'd54: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [15:8] <= write_data_i[15:8]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [23:16] <= write_data_i[23:16]; + end + 6'd55: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [7:0] <= write_data_i[7:0]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [15:8] <= write_data_i[15:8]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [23:16] <= write_data_i[23:16]; + end + 6'd56: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [31:24] <= write_data_i[31:24]; + end + 6'd57: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [7:0] <= write_data_i[7:0]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [31:24] <= write_data_i[31:24]; + end + 6'd58: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [15:8] <= write_data_i[15:8]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [31:24] <= write_data_i[31:24]; + end + 6'd59: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [7:0] <= write_data_i[7:0]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [15:8] <= write_data_i[15:8]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [31:24] <= write_data_i[31:24]; + end + 6'd60: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [23:16] <= write_data_i[23:16]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [31:24] <= write_data_i[31:24]; + end + 6'd61: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [7:0] <= write_data_i[7:0]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [23:16] <= write_data_i[23:16]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [31:24] <= write_data_i[31:24]; + end + 6'd62: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [15:8] <= write_data_i[15:8]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [23:16] <= write_data_i[23:16]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [31:24] <= write_data_i[31:24]; + end + 6'd63: begin + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [7:0] <= write_data_i[7:0]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [15:8] <= write_data_i[15:8]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [23:16] <= write_data_i[23:16]; + ram [addr_i[$clog2(DATA_MEM_SIZE_WORDS)-1:32'ha&32'h2]] [31:24] <= write_data_i[31:24]; + end + endcase end endmodule