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ЛР15-16. Исправление тестбенчей.

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Fe1LDr
2024-05-27 19:18:48 +03:00
parent f7ab67dfed
commit af721e3efa
4 changed files with 139 additions and 81 deletions
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12
Labs/16. Coremark/tb_coremark.sv
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@@ -10,7 +10,7 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
*/
module tb_coremark();
logic clk10mhz_i;
logic clk100mhz_i;
logic aresetn_i;
logic rx_i;
logic tx_o;
@@ -18,18 +18,19 @@ module tb_coremark();
logic rst_i;
assign aresetn_i = !rst_i;
assign clk10mhz_i = clk_i;
logic rx_busy, rx_valid, tx_busy, tx_valid;
logic [7:0] rx_data, tx_data;
always #50ns clk_i = !clk_i;
always #5ns clk100mhz_i = !clk100mhz_i;
byte coremark_msg[103];
integer coremark_cntr;
initial begin
$timeformat(-9, 2, " ns", 3);
clk100mhz_i = 0;
clk_i = 0;
rst_i <= 0;
@(posedge clk_i);
@@ -58,7 +59,12 @@ module tb_coremark();
end
initial #500ms $finish();
riscv_top_asic DUT(.clk10mhz_i, .aresetn_i, .rx_i, .tx_o);
riscv_unit DUT(
.clk_i (clk100mhz_i),
.resetn_i (aresetn_i),
.rx_i (rx_i),
.tx_o (tx_o)
);
uart_rx rx(
.clk_i (clk_i ),

6
Labs/16. Coremark/tb_timer.sv
View File

@@ -21,9 +21,9 @@ module tb_timer();
logic interrupt_request_o;
localparam SYS_CNT_ADDR = 32'h0000_0000;
localparam DELAY_ADDR = 32'h0000_0004;
localparam MODE_ADDR = 32'h0000_0008;
localparam REP_CNT_ADDR = 32'h0000_000C;
localparam DELAY_ADDR = 32'h0000_0008;
localparam MODE_ADDR = 32'h0000_0010;
localparam REP_CNT_ADDR = 32'h0000_0014;
localparam RST_ADDR = 32'h0000_0024;
localparam OFF = 32'd0;