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ЛР15-16. Исправление тестбенчей.

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Fe1LDr
2024-05-27 19:18:48 +03:00
parent f7ab67dfed
commit af721e3efa
4 changed files with 139 additions and 81 deletions
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17
Labs/15. Programming device/tb_bluster.sv
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@@ -65,6 +65,19 @@ module tb_blaster();
instr_size = instr_mem_byte.size();
data_size = data_mem_byte.size();
tiff_size = tiff_mem_byte.size();
/*
RCV_NEXT_COMMAND
*/
flash_addr = 32'h0000;
for(int i = MSG_ACK_SIZE-1; i >= 0; i--) begin
tx_data = flash_addr[i];
tx_valid = 1'b1;
@(posedge clk_i);
tx_valid = 1'b0;
@(posedge clk_i);
while(tx_busy) @(posedge clk_i);
end
/*
INIT_MSG
@@ -317,7 +330,7 @@ module tb_blaster();
while(tx_busy) @(posedge clk_i);
end
assert(!pc_reset_o)
assert(!core_reset_o)
else $error("reset is not equal zero at the end");
// ----------------------------------------------
@@ -355,7 +368,7 @@ uart_tx tx(
rw_instr_mem imem(
.clk_i (clk_i ) ,
.addr_i (instr_addr_i ) ,
.read_addr_i (instr_addr_i ) ,
.read_data_o (instr_rdata_o ) ,
.write_addr_i (instr_addr_o ) ,
.write_data_i (instr_wdata_o ) ,