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diff --git a/.pic/Labs/lab_01_adder/fig_06.drawio.png b/.pic/Labs/lab_01_adder/fig_06.png
similarity index 100%
rename from .pic/Labs/lab_01_adder/fig_06.drawio.png
rename to .pic/Labs/lab_01_adder/fig_06.png
diff --git a/Introduction/Implementation steps.md b/Introduction/Implementation steps.md
index e886cda..0f6cb66 100644
--- a/Introduction/Implementation steps.md	
+++ b/Introduction/Implementation steps.md	
@@ -16,7 +16,7 @@
 
 Допустим, мы хотим реализовать следующую цифровую схему:
 
-![../.pic/Introduction/Implementation%20steps/fig_01.drawio.png](../.pic/Introduction/Implementation%20steps/fig_01.drawio.png)
+![../.pic/Introduction/Implementation%20steps/fig_01.drawio.svg](../.pic/Introduction/Implementation%20steps/fig_01.drawio.svg)
 
 Её можно описать следующим **SystemVerilog**-кодом:
 
diff --git a/Introduction/What is HDL.md b/Introduction/What is HDL.md
index d1fb40f..dd2fd1d 100644
--- a/Introduction/What is HDL.md	
+++ b/Introduction/What is HDL.md	
@@ -31,7 +31,7 @@ _Рисунок 4. Структурная схема блока аппаратн
 В какой-то момент, инженеры поняли, что проще описать цифровую схему в текстовом представлении, нежели в графическом.  
 Как можно описать цифровую схему текстом? Рассмотрим цифровую схему полусумматора:
 
-![Схема полусумматора](../.pic/Labs/lab_01_adder/fig_01.drawio.png)
+![Схема полусумматора](../.pic/Labs/lab_01_adder/fig_01.drawio.svg)
 
 _Рисунок 5. Цифровая схема полусумматора._
 
diff --git a/Labs/01. Adder/README.md b/Labs/01. Adder/README.md
index 11f399f..d190c8f 100644
--- a/Labs/01. Adder/README.md	
+++ b/Labs/01. Adder/README.md	
@@ -217,7 +217,7 @@ _Рисунок 5. Схема четырехбитного сумматора._
 
 Для того, чтобы описать четырехбитный сумматор, необходимо подключить четыре однобитных подобно тому, как было описано в [`документе`](../../Basic%20Verilog%20structures/Modules.md#иерархия-модулей), который вы изучали перед лабораторной работой.
 
-![../../.pic/Labs/lab_01_adder/fig_06.drawio.png](../../.pic/Labs/lab_01_adder/fig_06.drawio.png)
+![../../.pic/Labs/lab_01_adder/fig_06.png](../../.pic/Labs/lab_01_adder/fig_06.png)
 
 _Рисунок 6. Схема четырехбитного сумматора, сгенерированная САПР Vivado._
 
diff --git a/Labs/03. Register file and memory/README.md b/Labs/03. Register file and memory/README.md
index ca0c7a9..c4922e1 100644
--- a/Labs/03. Register file and memory/README.md	
+++ b/Labs/03. Register file and memory/README.md	
@@ -50,7 +50,7 @@
 
 Так же возможна реализация, в которой вход `write_data` и выход `read_data` объединены в единый вход/выход `data`. В этом случае операции чтения и записи разделены во времени и используют для этого один единый порт ввода-вывода (`inout`, двунаправленный порт) `data`.
 
-![../../.pic/Labs/lab_03_memory/fig_01.drawio.png](../../.pic/Labs/lab_03_memory/fig_01.drawio.svg)
+![../../.pic/Labs/lab_03_memory/fig_01.drawio.svg](../../.pic/Labs/lab_03_memory/fig_01.drawio.svg)
 
 _Рисунок 1. Примеры блоков ПЗУ и ОЗУ._
 
diff --git a/Labs/12. Peripheral units/README.md b/Labs/12. Peripheral units/README.md
index de56541..81d7f06 100644
--- a/Labs/12. Peripheral units/README.md	
+++ b/Labs/12. Peripheral units/README.md	
@@ -127,7 +127,7 @@ sys_clk_rst_gen divider(.ex_clk_i(clk_i),.ex_areset_n_i(resetn_i),.div_i(5),.sys
 
 ## Задание
 
-В рамках данной лабораторной работы необходимо реализовать модули-контроллеры двух периферийных устройств, реализующих управление в соответствии с приведенной ниже картой памяти и встроить их в процессорную систему, используя [_рис. 1_](../../.pic/Labs/lab_12_periph/fig_01.drawio.png). На карте приведено шесть периферийных устройств, вам необходимо взять только два из них. Какие именно — сообщит преподаватель.
+В рамках данной лабораторной работы необходимо реализовать модули-контроллеры двух периферийных устройств, реализующих управление в соответствии с приведенной ниже картой памяти и встроить их в процессорную систему, используя [_рис. 1_](../../.pic/Labs/lab_12_periph/fig_01.drawio.svg). На карте приведено шесть периферийных устройств, вам необходимо взять только два из них. Какие именно — сообщит преподаватель.
 
 ![Карта памяти](../../.pic/Labs/lab_12_periph/fig_02.png)
 
diff --git a/Labs/14. Programming device/README.md b/Labs/14. Programming device/README.md
index 8b7abf4..8614e6f 100644
--- a/Labs/14. Programming device/README.md	
+++ b/Labs/14. Programming device/README.md	
@@ -224,7 +224,7 @@ module rw_instr_mem(
 
 В основе работы модуля лежит конечный автомат со следующим графом перехода между состояниями:
 
-![../../.pic/Labs/lab_14_programming_device/fig_03.drawio.png](../../.pic/Labs/lab_14_programming_device/fig_03.drawio.png)
+![../../.pic/Labs/lab_14_programming_device/fig_03.drawio.svg](../../.pic/Labs/lab_14_programming_device/fig_03.drawio.svg)
 
 _Рисунок 3. Граф перехода между состояниями программатора._
 
@@ -473,7 +473,7 @@ endmodule
 
 ### Интеграция программатора в riscv_unit
 
-![../../.pic/Labs/lab_14_programming_device/fig_04.drawio.png](../../.pic/Labs/lab_14_programming_device/fig_04.drawio.png)
+![../../.pic/Labs/lab_14_programming_device/fig_04.drawio.svg](../../.pic/Labs/lab_14_programming_device/fig_04.drawio.svg)
 
 В первую очередь, необходимо заменить память инструкций и добавить новый модуль. После чего подключить программатор к памяти инструкций и мультиплексировать выход интерфейса памяти данных программатора с интерфейсом памяти данных LSU. Сигнал сброса процессора необходимо заменить на выход `core_reset_o`.