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ЛР10. Переделан тб к csr-контроллеру
This commit is contained in:
Andrei Solodovnikov
committed by
Andrei Solodovnikov
Andrei Solodovnikov
parent
56ddeec27d
commit
ae783b3c6b
@@ -9,7 +9,6 @@
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_csr();
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logic clk_i;
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logic rst_i;
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@@ -36,12 +35,11 @@ csr_controller dut(.*);
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always #5 clk_i <= ~clk_i;
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int err_count;
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bit not_stopped;
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initial begin
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$display("\n\n===========================\n\nPress button 'Run All' (F3)\n\n===========================\n\n");
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$stop();
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err_count = 0;
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not_stopped = 1;
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clk_i <= 0;
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rst_i <= 1'b1;
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repeat(2)@(posedge clk_i);
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@@ -66,8 +64,22 @@ initial begin
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csrr();
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csrw();
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trap();
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$display("Simulation finished. Number of errors: %d", err_count);
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$finish();
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if( !err_count ) $display("\n csr_controller SUCCESS!!!\n");
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$finish;
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end
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initial begin
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int not_stopped = 1;
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forever begin
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@(posedge clk_i);
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if((err_count >= 10) && not_stopped) begin
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$display("Simulation stopped after ten errors.");
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$stop();
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not_stopped = 0;
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end
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end
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end
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logic [31:0] data_ref;
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@@ -81,7 +93,9 @@ MCAUSE_ADDR};
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assign pc_ref = write_enable_i ? pc_i : pc_ref;
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assign mcause_ref = write_enable_i ? mcause_i : mcause_ref;
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always_comb begin
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if (rst_i) data_ref <= 0;
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if (write_enable_i)
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case(opcode_i)
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CSR_RW: data_ref <= #1 rs1_data_i;
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@@ -95,29 +109,28 @@ always_comb begin
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end
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task clear();
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opcode_i <= CSR_RW;
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rs1_data_i <= 0;
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imm_data_i <= 0;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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rst_i <= 1'b1;
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repeat(2)@(posedge clk_i);
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rst_i <= 1'b0;
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endtask
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//csrrw
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task csrrw();
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trap_i <= 0;
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opcode_i <= CSR_RW;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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opcode_i <= CSR_RW;
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addr_i <= addr[i];
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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//csrrs
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@@ -131,9 +144,12 @@ for (int i = 0; i<5; i = i+1) begin
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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//csrrc
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@@ -147,9 +163,12 @@ for (int i = 0; i<5; i = i+1) begin
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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@@ -164,9 +183,12 @@ for (int i = 0; i<5; i = i+1) begin
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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@@ -181,9 +203,12 @@ for (int i = 0; i<5; i = i+1) begin
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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@@ -198,9 +223,12 @@ for (int i = 0; i<5; i = i+1) begin
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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@@ -215,8 +243,12 @@ for (int i = 0; i<5; i = i+1) begin
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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@@ -231,8 +263,12 @@ for (int i = 0; i<5; i = i+1) begin
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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@@ -254,71 +290,124 @@ endtask
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task check_reg();
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trap_i <= 0;
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opcode_i <= 0;
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rs1_data_i <= 0;
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imm_data_i <= 0;
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write_enable_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RS;
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rs1_data_i <= 0;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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end
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endtask
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trap_a: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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(trap_i && (addr_i == MCAUSE_ADDR)) |-> ##1 (mepc_o === pc_i) && (read_data_o === mcause_i)
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($rose(trap_i) && (addr_i == MCAUSE_ADDR)) |-> ##1 (mepc_o === pc_i) && (read_data_o === mcause_i)
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)else begin
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err_count++;
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$error("\error write/read trap\n");
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if (mepc_o != pc_i)
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if (read_data_o != mcause_i)
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$error("Incorrect mepc and mcause on trap_i == 1: Time = %t. mepc_o(%h) != pc_i(%h), read_data_o(%h) != mcause_i(%h).\n", $time, mepc_o, pc_i, read_data_o, mcause_i);
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else
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$error("Incorrect mepc on trap_i == 1: Time = %t. mepc_o(%h) != pc_i(%h).\n", $time, mepc_o, pc_i);
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else
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$error("Incorrect mcause on trap_i == 1: Time = %t. read_data_o(%h) != mcause_i(%h).\n", $time, read_data_o, mcause_i);
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end
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csrrw_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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( (opcode_i === CSR_RW) && write_enable_i) |=> (read_data_o === data_ref) and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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( (opcode_i === CSR_RW) && $rose(write_enable_i)) |=> (read_data_o === data_ref)
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)else begin
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err_count++;
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$error("\error write/read csrrw\n");
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if (addr_i === MIE_ADDR) $error("Incorrect value in register mie by csrrw: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MEPC_ADDR) $error("Incorrect value in register mepc by csrrw: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MTVEC_ADDR) $error("Incorrect value in register mtvec by csrrw: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MCAUSE_ADDR) $error("Incorrect value in register mcause by csrrw: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MSCRATCH_ADDR) $error("Incorrect value in register mscratch by csrrw: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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end
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csrrs_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((opcode_i === CSR_RS) && write_enable_i) |=> read_data_o === data_ref and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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((opcode_i === CSR_RS) && $rose(write_enable_i)) |=> read_data_o === data_ref
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)else begin
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err_count++;
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$error("\error write/read csrrs\n");
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if (addr_i === MIE_ADDR) $error("Incorrect value in register mie by csrrs: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MEPC_ADDR) $error("Incorrect value in register mepc by csrrs: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MTVEC_ADDR) $error("Incorrect value in register mtvec by csrrs: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MCAUSE_ADDR) $error("Incorrect value in register mcause by csrrs: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MSCRATCH_ADDR) $error("Incorrect value in register mscratch by csrrs: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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end
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csrrc_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((opcode_i === CSR_RC) && write_enable_i) |=> read_data_o === data_ref and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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((opcode_i === CSR_RC) && $rose(write_enable_i)) |=> read_data_o === data_ref
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)else begin
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err_count++;
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$error("\error write/read csrrc\n");
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if (addr_i === MIE_ADDR) $error("Incorrect value in register mie by csrrc: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MEPC_ADDR) $error("Incorrect value in register mepc by csrrc: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MTVEC_ADDR) $error("Incorrect value in register mtvec by csrrc: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MCAUSE_ADDR) $error("Incorrect value in register mcause by csrrc: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MSCRATCH_ADDR) $error("Incorrect value in register mscratch by csrrc: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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end
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csrrwi_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((opcode_i === CSR_RWI) && write_enable_i) |=> read_data_o === data_ref and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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((opcode_i === CSR_RWI) && $rose(write_enable_i)) |=> read_data_o === data_ref
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)else begin
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err_count++;
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$error("\error write/read csrwi\n");
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if (addr_i === MIE_ADDR) $error("Incorrect value in register mie by csrrwi: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MEPC_ADDR) $error("Incorrect value in register mepc by csrrwi: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MTVEC_ADDR) $error("Incorrect value in register mtvec by csrrwi: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MCAUSE_ADDR) $error("Incorrect value in register mcause by csrrwi: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MSCRATCH_ADDR) $error("Incorrect value in register mscratch by csrrwi: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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end
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csrrci_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((opcode_i === CSR_RCI) && write_enable_i ) |=> read_data_o === data_ref and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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((opcode_i === CSR_RCI) && $rose(write_enable_i) ) |=> read_data_o === data_ref //and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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)else begin
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err_count++;
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$error("\error write/read csrrci\n");
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if (addr_i === MIE_ADDR) $error("Incorrect value in register mie by csrrci: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MEPC_ADDR) $error("Incorrect value in register mepc by csrrci: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MTVEC_ADDR) $error("Incorrect value in register mtvec by csrrci: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MCAUSE_ADDR) $error("Incorrect value in register mcause by csrrci: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MSCRATCH_ADDR) $error("Incorrect value in register mscratch by csrrci: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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end
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csrrsi_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((opcode_i === CSR_RSI) && write_enable_i) |=> read_data_o === data_ref and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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((opcode_i === CSR_RSI) && $rose(write_enable_i)) |=> read_data_o === data_ref //and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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)else begin
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err_count++;
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$error("\error write/read csrrsi\n");
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if (addr_i === MIE_ADDR) $error("Incorrect value in register mie by csrrsi: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MEPC_ADDR) $error("Incorrect value in register mepc by csrrsi: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MTVEC_ADDR) $error("Incorrect value in register mtvec by csrrsi: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MCAUSE_ADDR) $error("Incorrect value in register mcause by csrrsi: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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if (addr_i === MSCRATCH_ADDR) $error("Incorrect value in register mscratch by csrrsi: Time = %t. read_data_o(%h) != data_ref(%h).\n", $time, read_data_o, data_ref);
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end
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mie_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((addr_i === MIE_ADDR) && $rose(write_enable_i)) |=> (mie_o === data_ref)
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)else begin
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err_count++;
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$error("Incorrect signal mie_o: Time = %t. mie_o(%h) != data_ref(%h).\n", $time, mie_o, data_ref);
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end
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mepc_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((addr_i === MEPC_ADDR) && $rose(write_enable_i)) |=> (mepc_o === data_ref)
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)else begin
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err_count++;
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$error("Incorrect signal mepc_o: Time = %t. mepc_o(%h) != data_ref(%h).\n", $time, mepc_o, data_ref);
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end
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mtvec_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((addr_i === MTVEC_ADDR) && $rose(write_enable_i)) |=> (mtvec_o === data_ref)
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)else begin
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err_count++;
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$error("Incorrect signal mtvec_o: Time = %t. mtvec_o(%h) != data_ref(%h).\n", $time, mtvec_o, data_ref);
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end
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endmodule
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