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ЛР8. Добавление тб и готового модуля

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Andrei Solodovnikov
2023-10-30 20:04:11 +03:00
committed by Andrei Solodovnikov
parent f667837c48
commit aa381fc84e
4 changed files with 459 additions and 2 deletions
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10
Labs/Made-up modules/lab_07.ext_mem.sv
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@@ -1,3 +1,13 @@
//////////////////////////////////////////////////////////////////////////////////
// Company: MIET
// Engineer: Andrei Solodovnikov
// Module Name: ext_mem
// Project Name: RISCV_practicum
// Target Devices: Nexys A7-100T
// Description: external memory with byte_enable support
//
//////////////////////////////////////////////////////////////////////////////////
module ext_mem(
input logic clk_i,
input logic mem_req_i,