From a78e4a8ab0cfa5dc8fdadd08a5b4273cdc8934e9 Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <voultboy@yandex.ru>
Date: Tue, 3 Mar 2026 14:05:40 +0300
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---
 Basic Verilog structures/Multiplexors.md | 4 ----
 1 file changed, 4 deletions(-)

diff --git a/Basic Verilog structures/Multiplexors.md b/Basic Verilog structures/Multiplexors.md
index 31469f4..784cc02 100644
--- a/Basic Verilog structures/Multiplexors.md	
+++ b/Basic Verilog structures/Multiplexors.md	
@@ -226,7 +226,3 @@ assign one_bit_result = bus1024[select];
 Как описать на языке SystemVerilog следующую схему?
 
 ![../.pic/Basic%20Verilog%20structures/multiplexors/fig_05.drawio.svg](../.pic/Basic%20Verilog%20structures/multiplexors/fig_05.drawio.svg)
-
-## Список источников
-
-1. [Мультиплексор (электроника)](https://ru.wikipedia.org/wiki/Мультиплексор_(электроника)).