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WIP: APS cumulative update (#98)
* WIP: APS cumulative update * Update How FPGA works.md * Перенос раздела "Последовательностная логика" в отдельный док * Исправление картинки * Исправление оформления индексов * Переработка раздела Vivado Basics * Добавление картинки в руководство по созданию проекта * Исправление ссылок в анализе rtl * Обновление изображения в sequential logic * Исправление ссылок в bug hunting * Исправление ссылок * Рефактор руководства по прошивке ПЛИС * Mass update * Update fig_10 * Restore fig_02
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Andrei Solodovnikov
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391
Labs/10. Interrupt subsystem/lab_10.tb_irq.sv
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391
Labs/10. Interrupt subsystem/lab_10.tb_irq.sv
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Daniil Strelkov
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* Email(s) : @edu.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_10_tb_irq();
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logic clk_i;
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logic rst_i;
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logic exception_i;
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logic irq_req_i;
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logic mret_i;
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logic mie_i;
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logic irq_ret_o;
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logic [31:0] irq_cause_o;
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logic irq_o;
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string str;
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interrupt_controller dut(.*);
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int err_count;
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always #5 clk_i <= ~clk_i;
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initial begin
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$display("\n\n===========================\n\nPress button 'Run All' (F3)\n\n===========================\n\n");
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$stop();
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clk_i = '0;
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exception_i = '0;
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mret_i = '0;
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irq_req_i = '0;
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mie_i = '0;
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repeat(4)@(posedge clk_i);
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t1();
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t2();
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t3();
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t4();
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t5();
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t6();
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t7();
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t8();
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t9();
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t10();
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t11();
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t12();
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t13();
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t14();
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$display("Simulation finished. Number of errors: %d", err_count);
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$finish;
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end
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task reset();
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rst_i <= 1'b1;
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@(posedge clk_i);
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@(posedge clk_i);
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rst_i <= 1'b0;
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 0;
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endtask
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logic [1:0] k;
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task t1();
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$display("TEST 01. Granted request.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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#1
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eror_info(1,0);
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@(posedge clk_i);
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endtask
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task t2();
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$display("TEST 02. Forbidden request.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 0;
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#1
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eror_info(0,0);
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@(posedge clk_i);
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endtask
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task t3();
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$display("TEST 03. Another request while handling previous.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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#1
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eror_info(0,0);
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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#1
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eror_info(0,0);
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@(posedge clk_i);
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endtask
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task t4();
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$display("TEST 04. Request while unhandled exception.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 1;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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#1
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eror_info(0,0);
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 1;
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irq_req_i = 0;
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mie_i = 1;
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#1
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eror_info(0,0);
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@(posedge clk_i);
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endtask
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task t5();
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$display("TEST 05. MRET while handling interrupt only.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 1;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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#1
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eror_info(0,1);
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@(posedge clk_i);
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endtask
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task t6();
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$display("TEST 06. MRET while handling exception only.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 1;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 1;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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eror_info(0,0);
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@(posedge clk_i);
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endtask
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task t7();
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$display("TEST 07. MRET while handling interrupt and exception.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 1;
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irq_req_i = 0;
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mie_i = 1;
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#1
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eror_info(0,0);
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@(posedge clk_i)
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mret_i = 1;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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eror_info(0,0);
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@(posedge clk_i);
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endtask
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task t8();
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$display("TEST 08. Two MRETs while handling interrupt and exception.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 1;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 1;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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#1
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@(posedge clk_i);
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mret_i = 1;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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#1
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eror_info(0,1);
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@(posedge clk_i);
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endtask
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task t9();
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$display("TEST 09. MRET while unhandled interrupt and subsequent request.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 1;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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#1
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eror_info(1,0);
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@(posedge clk_i);
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endtask
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task t10();
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$display("TEST 10. MRET while unhandled exception and subsequent request.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 1;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 1;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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#1
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eror_info(1,0);
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@(posedge clk_i);
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endtask
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task t11();
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$display("TEST 11. MRET while unhandled interrupt and exception and subsequent request.");
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reset();
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@(posedge clk_i);
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mret_i <= 0;
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exception_i <= 0;
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irq_req_i <= 1;
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mie_i <= 1;
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@(posedge clk_i);
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mret_i <= 0;
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exception_i <= 1;
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irq_req_i <= 0;
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mie_i <= 1;
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@(posedge clk_i);
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mret_i <= 1;
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exception_i <= 0;
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irq_req_i <= 0;
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mie_i <= 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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#1
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eror_info(0,0);
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@(posedge clk_i);
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endtask
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task t12();
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$display("TEST 12. Two MRETs while unhandled interrupt and exception and susbsequent request.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 1;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 1;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 1;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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#1
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str = "request interrupt after 2 mret for interrupt and exception";
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eror_info(1,0);
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@(posedge clk_i);
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endtask
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task t13();
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$display("TEST 13. Request next cycle after excetion.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 1;
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irq_req_i = 0;
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mie_i = 1;
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 1;
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mie_i = 1;
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#1
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eror_info(0,0);
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@(posedge clk_i);
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endtask
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task t14();
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$display("TEST 14. Request same cycle with the exception.");
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reset();
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@(posedge clk_i);
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mret_i = 0;
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exception_i = 1;
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irq_req_i = 1;
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mie_i = 1;
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#1
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eror_info(0,0);
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@(posedge clk_i);
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endtask
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//logic irq, irq_ret;
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task eror_info(irq, irq_ret);
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if (irq_o!=irq) begin $error("invalid irq_o = %b, expected value %b." , irq_o, irq ); err_count++; end
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if (irq_ret_o!=irq_ret) begin $error("invalid irq_ret_o = %b, expected value %b." , irq_ret_o, irq_ret); err_count++; end
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if (irq_cause_o!=32'h8000_0010) begin $error("invalid irq_cause_o = %h, expected value 32'h8000_0010.", irq_cause_o ); err_count++; end
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endtask
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endmodule
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