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WIP: APS cumulative update (#98)
* WIP: APS cumulative update * Update How FPGA works.md * Перенос раздела "Последовательностная логика" в отдельный док * Исправление картинки * Исправление оформления индексов * Переработка раздела Vivado Basics * Добавление картинки в руководство по созданию проекта * Исправление ссылок в анализе rtl * Обновление изображения в sequential logic * Исправление ссылок в bug hunting * Исправление ссылок * Рефактор руководства по прошивке ПЛИС * Mass update * Update fig_10 * Restore fig_02
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Andrei Solodovnikov
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406
Labs/10. Interrupt subsystem/lab_10.tb_csr.sv
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406
Labs/10. Interrupt subsystem/lab_10.tb_csr.sv
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Daniil Strelkov
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* Email(s) : @edu.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_10_tb_csr();
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logic clk_i;
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logic rst_i;
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logic trap_i;
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logic [ 2:0] opcode_i;
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logic [11:0] addr_i;
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logic [31:0] pc_i;
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logic [31:0] mcause_i;
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logic [31:0] rs1_data_i;
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logic [31:0] imm_data_i;
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logic write_enable_i;
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logic [31:0] read_data_o;
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logic [31:0] mie_o;
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logic [31:0] mepc_o;
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logic [31:0] mtvec_o;
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import csr_pkg::*;
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csr_controller dut(.*);
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always #5 clk_i <= ~clk_i;
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int err_count;
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initial begin
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$display("\n\n===========================\n\nPress button 'Run All' (F3)\n\n===========================\n\n");
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$stop();
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err_count = 0;
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clk_i <= 0;
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rst_i <= 1'b1;
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repeat(2)@(posedge clk_i);
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rst_i <= 1'b0;
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end
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initial begin
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opcode_i = '0;
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addr_i = '0;
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pc_i = '0;
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mcause_i = '0;
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rs1_data_i = '0;
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imm_data_i = '0;
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trap_i = '0;
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repeat(4)@(posedge clk_i);
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csrrw();
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csrrs();
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csrrc();
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csrrwi();
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csrrsi();
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csrrci();
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csrr();
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csrw();
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trap();
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seq_write();
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$display("Simulation finished. Number of errors: %d", err_count);
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if( !err_count ) $display("\n csr_controller SUCCESS!!!\n");
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$finish;
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end
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initial begin
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automatic int not_stopped = 1;
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forever begin
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@(posedge clk_i);
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if((err_count >= 10) && not_stopped) begin
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$display("Simulation stopped after ten errors.");
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$stop();
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not_stopped = 0;
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end
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end
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end
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logic [31:0] data_ref;
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logic [31:0] pc_ref;
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logic [31:0] mcause_ref;
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logic [11:0] addr [0:4] = { MIE_ADDR,
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MTVEC_ADDR,
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MSCRATCH_ADDR,
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MEPC_ADDR,
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MCAUSE_ADDR};
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task seq_write();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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@(posedge clk_i);
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addr_i <= addr[i];
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opcode_i <= CSR_RW;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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assign pc_ref = write_enable_i ? pc_i : pc_ref;
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assign mcause_ref = write_enable_i ? mcause_i : mcause_ref;
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always_ff @(posedge clk_i) begin
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if (rst_i) data_ref = 0;
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if (write_enable_i)
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case(opcode_i)
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CSR_RW: data_ref = rs1_data_i;
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CSR_RS: data_ref = rs1_data_i | read_data_o;
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CSR_RC: data_ref = ~rs1_data_i & read_data_o;
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CSR_RWI: data_ref = imm_data_i;
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CSR_RSI: data_ref = imm_data_i | read_data_o;
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CSR_RCI: data_ref = ~imm_data_i & read_data_o;
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default: data_ref = data_ref;
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endcase
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end
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task clear();
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rst_i <= 1'b1;
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repeat(2)@(posedge clk_i);
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rst_i <= 1'b0;
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endtask
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//csrrw
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task csrrw();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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opcode_i <= CSR_RW;
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addr_i <= addr[i];
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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//csrrs
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task csrrs();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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opcode_i <= CSR_RS;
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addr_i <= addr[i];
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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//csrrc
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task csrrc();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RC;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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//csrrwi
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task csrrwi();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RWI;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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//csrrsi
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task csrrsi();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RSI;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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//csrrci
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task csrrci();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RCI;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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//csrr
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task csrr();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RS;
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rs1_data_i <= 0;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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//csrw
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task csrw();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RW;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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@(posedge clk_i);
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end
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endtask
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//trap
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task trap();
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repeat(100) begin
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opcode_i <= $random;
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addr_i <= MCAUSE_ADDR;
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pc_i <= $random;
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mcause_i <= $random;
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write_enable_i <= 0;
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trap_i <= 1;
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@(posedge clk_i);
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trap_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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endtask
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task check_reg();
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trap_i <= 0;
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opcode_i <= 0;
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rs1_data_i <= 0;
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imm_data_i <= 0;
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write_enable_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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addr_i <= addr[i];
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@(posedge clk_i);
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end
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endtask
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trap_mepc_a: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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$rose(trap_i) |-> ##1 (mepc_o === pc_i)
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)else begin
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err_count++;
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$display("Incorrect mepc on trap : mepc_o = %08h while it should be %08h.\n", mepc_o, pc_i);
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end
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trap_mcause_a: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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($rose(trap_i) && (addr_i == MCAUSE_ADDR)) |-> ##1 (read_data_o === mcause_i)
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)else begin
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err_count++;
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$display("Incorrect mcause on trap : read_data_o = %08h while it should be %08h.\n", read_data_o, mcause_i);
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end
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string reg_name;
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string padding;
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csr_read_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i || $changed(addr_i, @(posedge clk_i)))
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( (opcode_i inside {CSR_RW, CSR_RS, CSR_RC, CSR_RWI, CSR_RSI, CSR_RCI} ) && write_enable_i) |=> (read_data_o === data_ref)
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)else begin
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err_count++;
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case(addr_i)
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MIE_ADDR : reg_name = "mie ";
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MTVEC_ADDR : reg_name = "mtvec ";
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MSCRATCH_ADDR : reg_name = "mscratch";
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MEPC_ADDR : reg_name = "mepc ";
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MCAUSE_ADDR : reg_name = "mcause ";
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default : reg_name = "ill_addr";
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endcase
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$display("Incorrect read from %s: read_data_o = %08h while it should be %08h.\n", reg_name, read_data_o, data_ref);
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end
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mie_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((addr_i === MIE_ADDR) && $rose(write_enable_i)) |=> (mie_o === data_ref)
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)else begin
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err_count++;
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$display("Incorrect value of mie_o : mie_o = %08h while if should be %08h.\n", mie_o, data_ref);
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end
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mepc_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((addr_i === MEPC_ADDR) && $rose(write_enable_i)) |=> (mepc_o === data_ref)
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)else begin
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err_count++;
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$display("Incorrect value of mepc_o : mepc_o = %08h while if should be %08h.\n", mepc_o, data_ref);
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end
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mtvec_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((addr_i === MTVEC_ADDR) && $rose(write_enable_i)) |=> (mtvec_o === data_ref)
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)else begin
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err_count++;
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$display("Incorrect value of mtvec_o : mtvec_o = %08h while if should be %08h.\n", mtvec_o, data_ref);
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end
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mepc_stability_a: assert property (
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@(posedge clk_i) disable iff (rst_i)
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!(trap_i | (write_enable_i & (addr_i === MEPC_ADDR))) |=> $stable(mepc_o)
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)else begin
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err_count++;
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$display("Illegal change of mepc val : it should be stable while trap_i = 0 and there is no CSR instruction at MEPC_ADDR");
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end
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mtvec_stability_a: assert property (
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@(posedge clk_i) disable iff (rst_i)
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!(write_enable_i & (addr_i === MTVEC_ADDR)) |=> $stable(mtvec_o)
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)else begin
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err_count++;
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$display("Illegal change of mtvec val : it should be stable while there is no CSR instruction at MTVEC_ADDR");
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end
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mie_stability_a: assert property (
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@(posedge clk_i) disable iff (rst_i)
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!(write_enable_i & (addr_i === MIE_ADDR)) |=> $stable(mie_o)
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)else begin
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err_count++;
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$display("Illegal change of mie val : it should be stable while there is no CSR instruction at MIE_ADDR");
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end
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endmodule
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