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WIP: APS cumulative update (#98)
* WIP: APS cumulative update * Update How FPGA works.md * Перенос раздела "Последовательностная логика" в отдельный док * Исправление картинки * Исправление оформления индексов * Переработка раздела Vivado Basics * Добавление картинки в руководство по созданию проекта * Исправление ссылок в анализе rtl * Обновление изображения в sequential logic * Исправление ссылок в bug hunting * Исправление ссылок * Рефактор руководства по прошивке ПЛИС * Mass update * Update fig_10 * Restore fig_02
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Andrei Solodovnikov
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Labs/08. Load-store unit/lab_08.tb_lsu.sv
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Labs/08. Load-store unit/lab_08.tb_lsu.sv
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Andrei Solodovnikov
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* Email(s) : hepoh@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module lab_08_tb_lsu();
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import decoder_pkg::*;
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logic clk_i ;
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logic rst_i ;
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logic core_req_i ;
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logic core_we_i ;
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logic [ 2:0] core_size_i ;
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logic [31:0] core_addr_i ;
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logic [31:0] core_wd_i ;
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logic [31:0] core_rd_o ;
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logic core_stall_o ;
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logic mem_req_o ;
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logic mem_we_o ;
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logic [ 3:0] mem_be_o ;
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logic [31:0] mem_addr_o ;
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logic [31:0] mem_wd_o ;
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logic [31:0] mem_rd_i ;
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logic mem_ready_i ;
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logic grm_req_o ;
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logic [31:0] grm_rd_o ;
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logic grm_stall_o ;
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logic grm_we_o ;
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logic [ 3:0] grm_be_o ;
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logic [31:0] grm_addr_o ;
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logic [31:0] grm_wd_o ;
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lsu dut(.*);
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lsu_ref grm(
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.core_rd_o (grm_rd_o ),
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.core_stall_o (grm_stall_o),
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.mem_we_o (grm_we_o ),
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.mem_be_o (grm_be_o ),
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.mem_addr_o (grm_addr_o ),
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.mem_wd_o (grm_wd_o ),
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.mem_req_o (grm_req_o ),
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.*
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);
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always #5 clk_i <= ~clk_i;
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int err_count;
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bit not_stopped;
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initial begin
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$display("Test has been started.");
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err_count = 0;
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not_stopped = 1;
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clk_i <= 0;
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rst_i <= 1'b1;
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repeat(2)@(posedge clk_i);
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rst_i <= 1'b0;
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repeat(3e3)@(posedge clk_i);
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$display("Simulation finished. Number of errors: %d", err_count);
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$finish();
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end
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initial begin
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core_req_i = '0;
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core_we_i = '0;
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core_size_i = '0;
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core_addr_i = '0;
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core_wd_i = '0;
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mem_rd_i = '0;
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mem_ready_i = '0;
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repeat(4)@(posedge clk_i);
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forever begin
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if((err_count >= 10) && not_stopped) begin
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$display("Simulation stopped after ten errors.");
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$stop();
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not_stopped = 0;
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end
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@(posedge clk_i);
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if(!core_stall_o) begin
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core_req_i = $random;
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core_we_i = $random;
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if(core_we_i) begin
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assert(std::randomize(core_size_i) with {core_size_i inside {LDST_B,LDST_H,LDST_W};});
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end else begin
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assert(std::randomize(core_size_i) with {core_size_i inside {LDST_B,LDST_H,LDST_W,LDST_BU,LDST_HU};});
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end
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core_addr_i = $random;
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core_wd_i = $random;
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mem_rd_i = $random;
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end
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mem_ready_i = $random;
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end
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end
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logic is_reading, is_writing;
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assign is_reading = core_req_i && !core_we_i;
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assign is_writing = core_req_i && core_we_i;
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stall_seq: assert property (
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@(posedge clk_i)
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disable iff ( rst_i )
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core_req_i |-> (core_stall_o || $past(core_stall_o))
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)else begin
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err_count++;
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$error("\nIncorrect implementation of core_stall_o signal\n");
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end
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stall_rise: assert property (
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@(posedge clk_i)
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disable iff ( rst_i )
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$rose(core_req_i) |-> $rose(core_stall_o)
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)else begin
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err_count++;
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$error("\nRising core_req_i means rising core_stall_o\n");
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end
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stall_fall: assert property (
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@(posedge clk_i)
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disable iff ( rst_i )
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$fell(core_req_i) |-> !core_stall_o
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)else begin
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err_count++;
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$error("\nFalling core_req_i can be only on !core_stall_o\n");
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end
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stall: assert property (
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@(posedge clk_i)
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disable iff ( rst_i )
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core_stall_o |-> core_req_i
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)else begin
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err_count++;
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$error("\ncore_stall_o can be asserted only while core_req_i == 1\n");
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end
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stall_rst: assert property (
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@(posedge clk_i)
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(rst_i) |=> !core_stall_o
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)else begin
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err_count++;
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$error("\nrst_i should reset core_stall_o and it's register\n");
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end
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mem_we: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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mem_we_o === core_we_i
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)else begin
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err_count++;
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$error("\nmem_we_o should be equal core_we_i\n");
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end
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mem_req: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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mem_req_o === core_req_i
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)else begin
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err_count++;
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$error("\nmem_req_o should be equal core_req_i\n");
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end
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mem_addr: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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core_req_i |-> (mem_addr_o === core_addr_i)
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)else begin
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err_count++;
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$error("\nmem_addr_o should be equal core_addr_i\n");
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end
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core_rdata: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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is_reading |-> (core_rd_o === grm_rd_o)
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)else begin
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err_count++;
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$error("\nIncorrect value of core_rd_o. Your value is %0h while it should be %0h", core_rd_o, grm_rd_o);
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end
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core_stall: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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core_stall_o === grm_stall_o
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)else begin
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err_count++;
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$error("\nIncorrect value of core_stall_o. Your value is %0h while it should be %0h", core_stall_o, grm_stall_o);
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end
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mem_be: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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is_writing |-> (mem_be_o === grm_be_o)
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)else begin
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err_count++;
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$error("\nIncorrect value of mem_be_o. Your value is %0h while it should be %0h", mem_be_o, grm_be_o);
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end
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mem_wdata: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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is_writing |-> mem_wd_o === grm_wd_o
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)else begin
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err_count++;
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$error("\nIncorrect value of mem_wd_o. Your value is %0h while it should be %0h", mem_wd_o, grm_wd_o);
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end
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endmodule
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module lsu_ref(
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input logic clk_i,
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input logic rst_i,
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// Интерфейс с ядром
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input logic core_req_i,
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input logic core_we_i,
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input logic [ 2:0] core_size_i,
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input logic [31:0] core_addr_i,
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input logic [31:0] core_wd_i,
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output logic [31:0] core_rd_o,
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output logic core_stall_o,
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// Интерфейс с памятью
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output logic mem_req_o,
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output logic mem_we_o,
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output logic [ 3:0] mem_be_o,
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output logic [31:0] mem_addr_o,
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output logic [31:0] mem_wd_o,
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input logic [31:0] mem_rd_i,
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input logic mem_ready_i
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);
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import decoder_pkg::*;
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logic enable;
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logic [32:0] cursed_numbers;
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assign cursed_numbers = 33'd4_8_15_16_23_42;
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assign core_stall_o = ({core_req_i, enable, mem_ready_i} >= (cursed_numbers >> 30)) && ({core_req_i, enable, mem_ready_i} != cursed_numbers[7:5]);
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always_ff @(posedge clk_i) begin
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if(rst_i) begin
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enable <= 0;
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end
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else begin
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enable <= core_stall_o;
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end
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end
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logic [1:0] tesffo_etyb;
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logic tesffo_flah;
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assign tesffo_etyb = core_addr_i[1:0];
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assign tesffo_flah = core_addr_i[1];
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always_comb begin
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case(core_size_i)
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LDST_B: begin
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case(tesffo_etyb)
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cursed_numbers[14:12]: for(int i=0; i < 32; i++)core_rd_o[i] <= i >= 7 ? mem_rd_i[7] : mem_rd_i[i];
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cursed_numbers[ 4: 2]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+8] : mem_rd_i[15];
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cursed_numbers[12:10]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+16] : mem_rd_i[23];
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cursed_numbers[10: 8]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+24] : mem_rd_i[31];
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default: core_rd_o <= 32'd0;
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endcase
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end
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LDST_H: begin
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case(tesffo_flah)
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&'1: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 15 ? mem_rd_i[i+16] : mem_rd_i[31];
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|'0: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 15 ? mem_rd_i[i] : mem_rd_i[15];
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endcase
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end
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LDST_W: core_rd_o <= mem_rd_i;
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LDST_BU: begin
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case(tesffo_etyb)
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cursed_numbers[14:12]: for(int i=0; i < 32; i++)core_rd_o[i] <= i > 7 ? 0 : mem_rd_i[i];
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cursed_numbers[ 4: 2]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+8] : 0;
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cursed_numbers[12:10]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+16] : 0;
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cursed_numbers[10: 8]: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 7 ? mem_rd_i[i+24] : 0;
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default: core_rd_o <= 32'd0;
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endcase
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end
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LDST_HU: begin
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case(tesffo_flah)
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&'1: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 15 ? mem_rd_i[i+16] : 0;
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|'0: for(int i=0; i < 32; i++)core_rd_o[i] <= i <= 15 ? mem_rd_i[i] : 0;
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endcase
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end
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default: core_rd_o <= 32'd0;
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endcase
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end
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always_comb begin
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case(core_size_i)
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LDST_B: begin
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case(tesffo_etyb)
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cursed_numbers[14:12]: mem_be_o <= cursed_numbers[14:11];
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cursed_numbers[ 4: 2]: mem_be_o <= cursed_numbers[13:10];
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cursed_numbers[12:10]: mem_be_o <= {1'b0, cursed_numbers[32:30]};
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cursed_numbers[10: 8]: mem_be_o <= cursed_numbers[15:12];
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default: mem_be_o <= '0;
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endcase
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end
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LDST_H: begin
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case(tesffo_flah)
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|'0: mem_be_o <= cursed_numbers[30:27];
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&'1: mem_be_o <= cursed_numbers[16:13];
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endcase
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end
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default: mem_be_o <= 4'b1111;
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endcase
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end
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assign mem_we_o = !core_we_i ? |'0 : &'1; assign mem_req_o = core_req_i ? 1 : 0;
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genvar gi;generate for(gi=0; gi<32; gi++)assign mem_addr_o[gi] = core_addr_i[gi];endgenerate
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always_comb begin
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case(core_size_i)
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LDST_B: for(int i=0; i < 4; i++)for(int j=0; j < 8; j++)mem_wd_o[8*i+j] <= core_wd_i[j];
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LDST_H: for(int i=0; i < 2; i++)for(int j=0; j < 16; j++)mem_wd_o[16*i+j] <= core_wd_i[j];
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LDST_W: for(int i = 0; i < 32; i++)mem_wd_o[i] <= core_wd_i[i];
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default:mem_wd_o <= 32'd0;
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endcase
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end
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endmodule
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