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brosandr.lab_02_alu (#62)
* Feat(02_Alu):Перепиcывание board модуля * Fix(02_Alu):Замена .v->.sv в board файле * Feat(pic/labs/board):Доб-ие пикчи alu_structure * Ref(pic/labs_board):Обн-ие nexys_alu_structure * Ref(pic/labs/board):Улуч-ие nexys_alu_struct * Ref(02_Alu/board):Замена назв-ий переменных в nexys_alu * Fix(02_Alu/board):Доб-ие @negedge arstn_i в регистр an * Ref(02_Alu/board):Переписывание форм-ия operand_* на assign * Ref(pic/labs/board):Rename ...svg->...drawio.svg * Ref(labs/02_Alu/nexys_alu):Перевод на bcd * Fix(labs/02_alu/nexys):Испр-ие вывода operand_a * Fix(labs/02_alu/nexys):Изм-ие разряд-ти bcd на 42 * Fix(.pic/labs/board/nexys_alu):Обн-ие разрядности * Ref(labs/02_alu/board):Обн-ие README * Ref(02_Alu/board):Дополнение описания оболочки * Ref(labs/02_alu_board):Различные улучшения md * Ref(labs_02_alu/board):Доб-ие точки в md * Repo(pic/labs/board):Уд-ие лишних картинок * Fix(labs/02_alu/board/md):Испр-ие alt названия * Ref(labs/02_alu/board):Перевод тире на юникод симв * Style(02_alu/board):Доб-ие абзаца после картинки * Fix(02_alu/board):Apply suggestions from code review Co-authored-by: Andrei Solodovnikov <VoultBoy@yandex.ru> * Ref(02_alu/board):Уд-ие переносов внутри абзаца * Style(02_alu):Доб-ие блейма * Fix(pic/02_alu):Поворот SE * Ref(pic/02_alu):Вырав-ие разярдностей и их цвета * Fix(02_alu/nexys):Испр-ие блейма * Ref(labs/02_alu/board):Переписывание bin2bcd * Fix(02_Alu):Apply suggestions from code review Co-authored-by: Andrei Solodovnikov <VoultBoy@yandex.ru> * Ref(pic/02_alu/alu_struct):Испр-ие шрифтов * Ref(pic/02_alu):Экспорт в svg * Ref(pic/02_alu/board):Обн-ие экспозиции nexys_alu * Ref(02_alu):Переделка маппинга свитчей в список * Ref(pic/02_alu/board):Подвижка боксов A,B,Sum * Ref(pic/02_alu/board):Замен цветов * Style(01_adder/board):Склеивание строк в абзацах * Ref(pic/02_alu/board):Испр-ие nexys_alu_struct * Fix(02_alu/board):Apply suggestions from code review Co-authored-by: Andrei Solodovnikov <VoultBoy@yandex.ru> * Repo(02_alu/board):Доб-ие шапки создателя --------- Co-authored-by: Andrei Solodovnikov <VoultBoy@yandex.ru>
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@@ -1,94 +1,181 @@
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* File : nexys_alu.sv
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Alexander Kharlamov
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* Email(s) : sasha_xarlamov@org.miet.ru
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See LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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module nexys_alu(
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input CLK100,
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input resetn,
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input [15:0] SW,
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output [15:0] LED,
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output CA, CB, CC, CD, CE, CF, CG,
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output [7:0] AN
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);
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import alu_opcodes_pkg::*;
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wire [4:0] operator_i;
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wire [31:0] operand_a_i;
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wire [31:0] operand_b_i;
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wire [31:0] result_o;
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wire comparison_result_o;
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localparam pwm = 1000;
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reg [9:0] counter;
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reg [3:0] semseg;
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reg [7:0] ANreg;
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reg CAr, CBr, CCr, CDr, CEr, CFr, CGr;
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reg [15:0] LEDr;
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reg minus;
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alu_riscv DUT
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(
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.alu_op_i (operator_i),
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.a_i (operand_a_i),
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.b_i (operand_b_i),
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.result_o (result_o),
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.flag_o (comparison_result_o)
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input logic clk_i,
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input logic arstn_i,
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input logic [15:0] sw_i,
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output logic [15:0] led_o,
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output logic ca_o,
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output logic cb_o,
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output logic cc_o,
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output logic cd_o,
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output logic ce_o,
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output logic cf_o,
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output logic cg_o,
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output logic dp_o,
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output logic [ 7:0] an_o
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);
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logic sign_on;
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assign sign_on = sw_i[5];
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assign operator_i = SW[4:0];
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assign operand_b_i = {{28{SW[10]}},SW[9:6]};
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assign operand_a_i = {{28{SW[15]}},SW[14:11]};
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logic sext_operand_a;
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assign sext_operand_a = sign_on;
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logic sext_operand_b;
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assign sext_operand_b = sign_on;
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assign LED[15:0] = LEDr[15:0];
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import alu_opcodes_pkg::*;
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assign AN[7:0] = ANreg[7:0];
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assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr};
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logic [4:0] operator;
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assign operator = sw_i[4:0];
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initial ANreg[7:0] = 8'b11111110;
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logic [31:0] operand_b;
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assign operand_b = {(sext_operand_b ? {27{sw_i[10]}} : 27'b0), sw_i[10: 6]};
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always @(posedge CLK100) begin
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if (!resetn) begin
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LEDr[15:0] <= 'b0;
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counter <= 'b0;
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ANreg[7:0] <= 8'b11111111;
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{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111;
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end
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else begin
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LEDr[14:0] <= result_o[14:0];
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LEDr[15] <= comparison_result_o;
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if (counter < pwm) counter = counter + 'b1;
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else begin
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counter = 'b0;
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ANreg[1] <= ANreg[0];
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ANreg[2] <= ANreg[1];
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ANreg[3] <= ANreg[2];
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ANreg[4] <= ANreg[3];
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ANreg[5] <= ANreg[4];
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ANreg[6] <= ANreg[5];
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ANreg[7] <= ANreg[6];
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ANreg[0] <= !(SW[5] && (ANreg[6:0] == 7'b1111111));
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end
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case (1'b0)
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ANreg[0]: semseg <= result_o[31] ? ( ~result_o + 1 ) % 4'd10: (result_o ) % 4'd10;
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ANreg[1]: semseg <= result_o[31] ? ((~result_o + 1) / 'd10 ) % 4'd10: (result_o / 'd10 ) % 4'd10;
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ANreg[2]: semseg <= result_o[31] ? ((~result_o + 1) / 'd100 ) % 4'd10: (result_o / 'd100 ) % 4'd10;
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ANreg[3]: semseg <= result_o[31] ? ((~result_o + 1) / 'd1000) % 4'd10: (result_o / 'd1000) % 4'd10;
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ANreg[4]: semseg <= operand_b_i[31] ? ( ~operand_b_i + 1 ) % 4'd10: (operand_b_i ) % 4'd10;
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ANreg[5]: semseg <= operand_b_i[31] ? ((~operand_b_i + 1) / 'd10) % 4'd10: (operand_b_i / 'd10) % 4'd10;
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ANreg[6]: semseg <= operand_a_i[31] ? ( ~operand_a_i + 1 ) % 4'd10: (operand_a_i ) % 4'd10;
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ANreg[7]: semseg <= operand_a_i[31] ? ((~operand_a_i + 1) / 'd10) % 4'd10: (operand_a_i / 'd10) % 4'd10;
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endcase
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minus <= (operator_i == ALU_ADD || operator_i == ALU_SUB || operator_i == ALU_SLTS || operator_i == ALU_SRA || operator_i == ALU_LTS || operator_i == ALU_GES);
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case (semseg)
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4'd0: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= (((!ANreg[5] & operand_b_i[31]) || (!ANreg[7] & operand_a_i[31]) || (!ANreg[3] & result_o[31])) && minus) ? 7'b1111110: 7'b0000001;
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4'd1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= (((!ANreg[5] & operand_b_i[31]) || (!ANreg[7] & operand_a_i[31]) || (!ANreg[3] & result_o[31])) && minus) ? 7'b1001110: 7'b1001111;
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4'd2: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0010010;
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4'd3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000110;
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4'd4: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001100;
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4'd5: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100;
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4'd6: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100000;
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4'd7: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001111;
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4'd8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000000;
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4'd9: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000100;
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endcase
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end
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end
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logic [31:0] operand_a;
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assign operand_a = {(sext_operand_a ? {27{sw_i[15]}} : 27'b0), sw_i[15:11]};
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logic [31:0] result;
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logic flag;
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alu_riscv alu_riscv (
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.alu_op_i (operator),
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.a_i (operand_a),
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.b_i (operand_b),
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.result_o (result),
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.flag_o (flag)
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);
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localparam int COUNTER_WIDTH = 10;
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logic [COUNTER_WIDTH-1:0] counter_next;
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logic [COUNTER_WIDTH-1:0] counter_ff;
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assign counter_next = counter_ff + COUNTER_WIDTH'('b1);
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) counter_ff <= '0;
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else counter_ff <= counter_next;
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end
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logic [7:0] an_ff;
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logic [7:0] an_next;
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logic an_en;
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assign an_next = {an_ff[$left(an_ff)-1:0], an_ff[$left(an_ff)]};
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assign an_en = ~|counter_ff;
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) an_ff <= ~8'b1;
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else if (an_en) an_ff <= an_next;
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end
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function automatic logic [6:0] hex2semseg(input logic [3:0] hex);
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unique case (hex)
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4'h0: return 7'b0000001;
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4'h1: return 7'b1001111;
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4'h2: return 7'b0010010;
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4'h3: return 7'b0000110;
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4'h4: return 7'b1001100;
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4'h5: return 7'b0100100;
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4'h6: return 7'b0100000;
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4'h7: return 7'b0001111;
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4'h8: return 7'b0000000;
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4'h9: return 7'b0000100;
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4'hA: return 7'b0001000;
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4'hB: return 7'b1100000;
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4'hC: return 7'b0110001;
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4'hD: return 7'b1000010;
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4'hE: return 7'b0110000;
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4'hF: return 7'b0111000;
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endcase
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endfunction
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logic is_result_negative;
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assign is_result_negative = result[$left(result)] & sign_on;
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logic is_operand_a_negative;
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assign is_operand_a_negative = operand_a[$left(operand_a)];
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logic is_operand_b_negative;
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assign is_operand_b_negative = operand_b[$left(operand_b)];
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logic [31:0] result_sign_regard;
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assign result_sign_regard = is_result_negative ? (~result + 32'b1) : result;
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logic [4:0] operand_a_sign_regard;
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assign operand_a_sign_regard = is_operand_a_negative ? (~operand_a[4:0] + 5'b1) : (operand_a[4:0]);
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logic [4:0] operand_b_sign_regard;
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assign operand_b_sign_regard = is_operand_b_negative ? (~operand_b[4:0] + 5'b1) : (operand_b[4:0]);
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logic [63:0] bcd_result;
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logic [11:0] bcd_operand_a;
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logic [11:0] bcd_operand_b;
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bin2bcd #($bits(result_sign_regard)) bin2bcd_result (
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.bin_i (result_sign_regard),
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.bcd_o (bcd_result )
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);
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bin2bcd #($bits(operand_a_sign_regard)) bin2bcd_operand_a (
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.bin_i (operand_a_sign_regard),
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.bcd_o (bcd_operand_a )
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);
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bin2bcd #($bits(operand_b_sign_regard)) bin2bcd_operand_b (
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.bin_i (operand_b_sign_regard),
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.bcd_o (bcd_operand_b )
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);
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localparam bit [6:0] MINUS = 7'b1111110;
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localparam bit [6:0] BLANK = 7'b1111111;
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logic [ 6:0] semseg;
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always_comb begin
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semseg = BLANK;
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unique case (1'b0)
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an_ff[0]: semseg = hex2semseg(bcd_result[ 3:0]);
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an_ff[1]: semseg = hex2semseg(bcd_result[ 7:4]);
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an_ff[2]: semseg = hex2semseg(bcd_result[11:8]);
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an_ff[3]: semseg = is_result_negative ? MINUS : BLANK;
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an_ff[4]: semseg = hex2semseg(bcd_operand_b[3:0]);
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an_ff[5]: semseg = (is_operand_b_negative ? MINUS : BLANK) & (|bcd_operand_b[5:4] ? hex2semseg({2'b0, bcd_operand_b[5:4]}) : BLANK);
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an_ff[6]: semseg = hex2semseg(bcd_operand_a[3:0]);
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an_ff[7]: semseg = (is_operand_a_negative ? MINUS : BLANK) & (|bcd_operand_a[5:4] ? hex2semseg({2'b0, bcd_operand_a[5:4]}) : BLANK);
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endcase
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end
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assign {ca_o, cb_o, cc_o, cd_o, ce_o, cf_o, cg_o} = semseg;
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assign dp_o = an_ff[6] ? 1'b1 : 1'b0;
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assign led_o[14:0] = result[14:0];
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assign led_o[15] = flag;
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assign an_o = an_ff;
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endmodule
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module bin2bcd #(
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parameter int IN_WIDTH = 32,
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localparam int OUT_WIDTH_DIGITS = (2 * IN_WIDTH + 3) / 4, // each byte is represented as 2 digits.
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// And ceiling
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localparam int OUT_WIDTH = 4 * OUT_WIDTH_DIGITS
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) (
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input logic [IN_WIDTH -1:0] bin_i,
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output logic [OUT_WIDTH-1:0] bcd_o
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);
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always @(bin_i) begin
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bcd_o = '0;
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for (int unsigned bit_number = 0; bit_number < IN_WIDTH; ++bit_number) begin // Iterate once for each bit in input number
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for (int unsigned digit_num = 0; digit_num < OUT_WIDTH_DIGITS; ++digit_num) begin
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if (bcd_o[4*digit_num+:4] >= 4'd5) bcd_o[4*digit_num+:4] = bcd_o[4*digit_num+:4] + 4'd3; // If any BCD digit is >= 5, add three
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end
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bcd_o = {bcd_o[$left(bcd_o)-1:0], bin_i[$left(bin_i)-bit_number]}; // Shift one bit, and shift in proper bit from input
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end
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end
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endmodule
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