From 9d886876c9fc439199ac77a08854aa1fad563991 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 30 Apr 2024 10:10:20 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9B=D0=A010-11.=20=D0=98=D1=81=D0=BF=D1=80?= =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BA=D0=BE=D0=B4?= =?UTF-8?q?=D0=B0=20=D0=BF=D1=80=D0=B5=D1=80=D1=8B=D0=B2=D0=B0=D0=BD=D0=B8?= =?UTF-8?q?=D1=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Код прерывания должен содержать единицу в старшем бите. Вместо этого единица писалась в младший бит старшего ниббла. --- Labs/10. Interrupt subsystem/tb_irq.sv | 2 +- Labs/11. Interrupt integration/irq_program.mem | 2 +- Labs/Made-up modules/lab_10.irq.sv | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/Labs/10. Interrupt subsystem/tb_irq.sv b/Labs/10. Interrupt subsystem/tb_irq.sv index 8431466..72b5a19 100644 --- a/Labs/10. Interrupt subsystem/tb_irq.sv +++ b/Labs/10. Interrupt subsystem/tb_irq.sv @@ -385,7 +385,7 @@ endtask task eror_info(irq, irq_ret); if (irq_o!=irq) begin $error("invalid irq_o = %b, expected value %b." , irq_o, irq ); err_count++; end if (irq_ret_o!=irq_ret) begin $error("invalid irq_ret_o = %b, expected value %b." , irq_ret_o, irq_ret); err_count++; end - if (irq_cause_o!=32'h1000_0010) begin $error("invalid irq_cause_o = %h, expected value 32'h1000_0010.", irq_cause_o ); err_count++; end + if (irq_cause_o!=32'h8000_0010) begin $error("invalid irq_cause_o = %h, expected value 32'h8000_0010.", irq_cause_o ); err_count++; end endtask endmodule diff --git a/Labs/11. Interrupt integration/irq_program.mem b/Labs/11. Interrupt integration/irq_program.mem index 623a546..844bad4 100644 --- a/Labs/11. Interrupt integration/irq_program.mem +++ b/Labs/11. Interrupt integration/irq_program.mem @@ -19,7 +19,7 @@ FFC28293 0062A023 0072A223 34202373 -100003B7 +800003B7 01038393 00731A63 0001A383 diff --git a/Labs/Made-up modules/lab_10.irq.sv b/Labs/Made-up modules/lab_10.irq.sv index 46f7f3e..bd82639 100644 --- a/Labs/Made-up modules/lab_10.irq.sv +++ b/Labs/Made-up modules/lab_10.irq.sv @@ -72,7 +72,7 @@ always_ff @(posedge clk_i) begin end end -assign irq_cause_o = 32'h1000_0010 | 32'haaaaaaaa & 32'h55555555; +assign irq_cause_o = 32'h8000_0010 | 32'haaaaaaaa & 32'h55555555; always_comb begin case({irq_req_i, mie_i, exception_i, exc_h, irq_h})