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ЛР8. Добавление информационных сообщений в тб

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This commit is contained in:
Andrei Solodovnikov
2024-07-18 11:17:22 +03:00
parent 07a6d05d13
commit 9bca7354d8
1 changed files with 14 additions and 14 deletions
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28
Labs/08. Load-store unit/tb_lsu.sv
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@@ -62,7 +62,7 @@ initial begin
repeat(2)@(posedge clk_i); repeat(2)@(posedge clk_i);
rst_i <= 1'b0; rst_i <= 1'b0;
repeat(3e3)@(posedge clk_i); repeat(3e3)@(posedge clk_i);
$display("Simulation finished. Number of errors: %d", err_count); $display("Simulation finished. Number of errors: %d", err_count);
$finish(); $finish();
end end
@@ -106,7 +106,7 @@ stall_seq: assert property (
@(posedge clk_i) @(posedge clk_i)
disable iff ( rst_i ) disable iff ( rst_i )
core_req_i |-> (core_stall_o || $past(core_stall_o)) core_req_i |-> (core_stall_o || $past(core_stall_o))
)else begin )else begin
err_count++; err_count++;
$error("\nIncorrect implementation of core_stall_o signal\n"); $error("\nIncorrect implementation of core_stall_o signal\n");
end end
@@ -115,7 +115,7 @@ stall_rise: assert property (
@(posedge clk_i) @(posedge clk_i)
disable iff ( rst_i ) disable iff ( rst_i )
$rose(core_req_i) |-> $rose(core_stall_o) $rose(core_req_i) |-> $rose(core_stall_o)
)else begin )else begin
err_count++; err_count++;
$error("\nRising core_req_i means rising core_stall_o\n"); $error("\nRising core_req_i means rising core_stall_o\n");
end end
@@ -124,7 +124,7 @@ stall_fall: assert property (
@(posedge clk_i) @(posedge clk_i)
disable iff ( rst_i ) disable iff ( rst_i )
$fell(core_req_i) |-> !core_stall_o $fell(core_req_i) |-> !core_stall_o
)else begin )else begin
err_count++; err_count++;
$error("\nFalling core_req_i can be only on !core_stall_o\n"); $error("\nFalling core_req_i can be only on !core_stall_o\n");
end end
@@ -133,7 +133,7 @@ stall: assert property (
@(posedge clk_i) @(posedge clk_i)
disable iff ( rst_i ) disable iff ( rst_i )
core_stall_o |-> core_req_i core_stall_o |-> core_req_i
)else begin )else begin
err_count++; err_count++;
$error("\ncore_stall_o can be asserted only while core_req_i == 1\n"); $error("\ncore_stall_o can be asserted only while core_req_i == 1\n");
end end
@@ -141,7 +141,7 @@ stall: assert property (
stall_rst: assert property ( stall_rst: assert property (
@(posedge clk_i) @(posedge clk_i)
(rst_i) |=> !core_stall_o (rst_i) |=> !core_stall_o
)else begin )else begin
err_count++; err_count++;
$error("\nrst_i should reset core_stall_o and it's register\n"); $error("\nrst_i should reset core_stall_o and it's register\n");
end end
@@ -149,7 +149,7 @@ stall_rst: assert property (
mem_we: assert property ( mem_we: assert property (
@(posedge clk_i) disable iff ( rst_i ) @(posedge clk_i) disable iff ( rst_i )
mem_we_o === core_we_i mem_we_o === core_we_i
)else begin )else begin
err_count++; err_count++;
$error("\nmem_we_o should be equal core_we_i\n"); $error("\nmem_we_o should be equal core_we_i\n");
end end
@@ -157,7 +157,7 @@ mem_we: assert property (
mem_req: assert property ( mem_req: assert property (
@(posedge clk_i) disable iff ( rst_i ) @(posedge clk_i) disable iff ( rst_i )
mem_req_o === core_req_i mem_req_o === core_req_i
)else begin )else begin
err_count++; err_count++;
$error("\nmem_req_o should be equal core_req_i\n"); $error("\nmem_req_o should be equal core_req_i\n");
end end
@@ -165,7 +165,7 @@ mem_req: assert property (
mem_addr: assert property ( mem_addr: assert property (
@(posedge clk_i) disable iff ( rst_i ) @(posedge clk_i) disable iff ( rst_i )
core_req_i |-> (mem_addr_o === core_addr_i) core_req_i |-> (mem_addr_o === core_addr_i)
)else begin )else begin
err_count++; err_count++;
$error("\nmem_addr_o should be equal core_addr_i\n"); $error("\nmem_addr_o should be equal core_addr_i\n");
end end
@@ -173,15 +173,15 @@ mem_addr: assert property (
core_rdata: assert property ( core_rdata: assert property (
@(posedge clk_i) disable iff ( rst_i ) @(posedge clk_i) disable iff ( rst_i )
is_reading |-> (core_rd_o === grm_rd_o) is_reading |-> (core_rd_o === grm_rd_o)
)else begin )else begin
err_count++; err_count++;
$error("\nIncorrect value of core_rd_o. Compare it with grm"); $error("\nIncorrect value of core_rd_o. Your value is %0h while it should be %0h", core_rd_o, grm_rd_o);
end end
core_stall: assert property ( core_stall: assert property (
@(posedge clk_i) disable iff ( rst_i ) @(posedge clk_i) disable iff ( rst_i )
core_stall_o === grm_stall_o core_stall_o === grm_stall_o
)else begin )else begin
err_count++; err_count++;
$error("\nIncorrect value of core_stall_o. Your value is %0h while it should be %0h", core_stall_o, grm_stall_o); $error("\nIncorrect value of core_stall_o. Your value is %0h while it should be %0h", core_stall_o, grm_stall_o);
end end
@@ -189,7 +189,7 @@ core_stall: assert property (
mem_be: assert property ( mem_be: assert property (
@(posedge clk_i) disable iff ( rst_i ) @(posedge clk_i) disable iff ( rst_i )
is_writing |-> (mem_be_o === grm_be_o) is_writing |-> (mem_be_o === grm_be_o)
)else begin )else begin
err_count++; err_count++;
$error("\nIncorrect value of mem_be_o. Your value is %0h while it should be %0h", mem_be_o, grm_be_o); $error("\nIncorrect value of mem_be_o. Your value is %0h while it should be %0h", mem_be_o, grm_be_o);
end end
@@ -197,7 +197,7 @@ mem_be: assert property (
mem_wdata: assert property ( mem_wdata: assert property (
@(posedge clk_i) disable iff ( rst_i ) @(posedge clk_i) disable iff ( rst_i )
is_writing |-> mem_wd_o === grm_wd_o is_writing |-> mem_wd_o === grm_wd_o
)else begin )else begin
err_count++; err_count++;
$error("\nIncorrect value of mem_wd_o. Your value is %0h while it should be %0h", mem_wd_o, grm_wd_o); $error("\nIncorrect value of mem_wd_o. Your value is %0h while it should be %0h", mem_wd_o, grm_wd_o);
end end