diff --git a/.pic/Labs/lab_10_irq/fig_03.drawio.svg b/.pic/Labs/lab_10_irq/fig_03.drawio.svg index cefa940..9e6e473 100644 --- a/.pic/Labs/lab_10_irq/fig_03.drawio.svg +++ b/.pic/Labs/lab_10_irq/fig_03.drawio.svg @@ -1,4 +1,4 @@ -

Main
Decoder

Main...

flag

flag
Register
File
Register...
imm_S
imm_S
imm_U
imm_U
4
4
0
0
RD1
RD1
RD2
RD2
gpr_we
gpr_we
WE
WE

clk_i

clk_i
wb_sel
wb_sel
 mem_size
 mem_size
mem_we
mem_we
alu_op
alu_op
b_sel
b_sel
a_sel
a_sel
jal
jal
b
b
instr
instr
RA1
RA1
RA2
RA2
WA
WA
WD
WD
[19:15]
[19:15]
[24:20]
[24:20]
[11:07]
[11:07]
[31:20]
[31:20]
[31:12], 12'h000
[31:12], 12'h000
[31:25][11:7]
[31:25][11:7]
[31][19:12][20][30:21],1'b0
[31][19:12][20][30:21],1'b0
[31][7][30:25][11:8],1'b0
[31][7][30:25][11:8],1'b0
imm_J
imm_J
imm_B
imm_B
4
4
PC
PC

clk_i

clk_i

rst_i

rst_i
jalr
jalr
ALU
ALU
SE
SE
SE
SE
+
+
mem_wd_o
mem_wd_o
instr_i
instr_i
mem_addr_o
mem_addr_o
instr_addr_o
instr_addr_o
mem_rd_i
mem_rd_i
mem_we_o
mem_we_o
mem_size_o
mem_size_o
instr_addr_o
instr_addr_o

instr_i

instr_i

mem_addr_o

mem_addr_o
mem_we_o
mem_we_o

mem_size_o

mem_size_o

rst_i

rst_i

clk_i

clk_i
SE
SE

0

1

0...

0

1

0...

flag

flag

32
/

32...

32
/

32...

32
/

32...

32
/

32...

32
/

32...

12
/

12...

12
/

12...

21
/

21...

13
/

13...

32
/

32...
mret
mret
SE
SE
mem_req 
mem_req 

mem_req_o

mem_req_o

imm_I

imm_I
— входные сигналы
— входные сигналы
выходные сигналы
— выходные сигналы
mem_req_o
mem_req_o

imm_I

imm_I
RD1
RD1

flag

flag
провода, разорванные        для удобства                    отображения схемы
— провода, разорванные        для удобства...
PC
PC

0
1
2
3
4

0...

0
1
2

0...
32
32
stall_i
stall_i
stall_i
stall_i

32
/

32...
2
2
3
3
3
3
5
5
mem_wd_o
mem_wd_o
mem_rd_i
mem_rd_i
wb_data
wb_data
wb_data
wb_data
wb_data
wb_data
32
32
PC
PC
2
2
0
0
2
2
1
1
csr_wd
csr_wd
 illegal_instr
 illegal_instr
CONTROL
STATUS
REGISTERS
CONTROL...
WE
WE

clk_i

clk_i
addr
addr
pc
pc
mcause
mcause
rs1_data
rs1_data
rst
rst
imm_data
imm_data
trap
trap
opcode
opcode
read_data
read_data
mie
mie
mepc
mepc
mtvec
mtvec
csr_we
csr_we
csr_op
csr_op
3
3
irq
irq
trap
trap
rst_i
rst_i
csr_wd
csr_wd
mie
mie
RD1
RD1
PC
PC
[19:15]
[19:15]
ZE
ZE

5
/

5...

32
/

32...

imm_Z

imm_Z

imm_Z

imm_Z

instr_i[31:20]

instr_i[31:20]
mret
mret
IRQ
CONTROLLER
IRQ...
exception_i
exception_i

clk_i

clk_i
irq_req_i
irq...
mie_i
mie_i
rst_i
rst_i
irq_cause_o
irq_cause...
irq_ret_o
irq_ret_o
rst_i
rst_i
trap
trap
mret
mret
irq
irq
irq_ret_o
irq_ret_o
irq_req_i
irq_req_i
mie[16]
mie[16]

imm_Z

imm_Z
csr_wd
csr_wd
irq
irq
trap
trap
mret
mret
mie
mie
irq_req_i
irq_req_i
irq_ret_o
irq_ret_o
jalr
jalr
PC
PC
jalr
jalr
32
32
32
32
32
32
32
32
12
12
32
32
32
32
32
32
32
32

1

0

1...
stall_i
stall_i
trap
trap
trap
trap
trap
trap
ill_instr
ill_ins...

0

1

0...
ill_instr
ill_ins...
32
32
32
32
irq
irq
ill_instr
ill_ins...
ill_instr
ill_ins...
mret_i
mret_i
irq_o
irq_o
32'h0000_0002
32'h0000_0002

imm_I

imm_I
+
+
RD1
RD1
jalr
jalr
{[31:1],1'b0}
{[31:1],1'b0}

1

0

1...

1

0

1...
trap
trap
trap
trap
en
en
rst
rst
Text is not SVG - cannot display
\ No newline at end of file +

Main
Decoder

flag

Register
File
imm_S
imm_U
4
0
RD1
RD2
gpr_we
WE

clk_i

wb_sel
 mem_size
mem_we
alu_op
b_sel
a_sel
jal
b
instr
RA1
RA2
WA
WD
[19:15]
[24:20]
[11:07]
[31:20]
[31:12], 12'h000
[31:25][11:7]
[31][19:12][20][30:21],1'b0
[31][7][30:25][11:8],1'b0
imm_J
imm_B
4
PC

clk_i

rst_i

jalr
ALU
SE
SE
+
mem_wd_o
instr_i
mem_addr_o
instr_addr_o
mem_rd_i
mem_we_o
mem_size_o
instr_addr_o

instr_i

mem_addr_o

mem_we_o

mem_size_o

rst_i

clk_i

SE

0

1

0

1

flag

32
/

32
/

32
/

32
/

32
/

12
/

12
/

21
/

13
/

32
/

mret
SE
mem_req 

mem_req_o

imm_I

— входные сигналы
выходные сигналы
mem_req_o

imm_I

RD1

flag

провода, разорванные        для удобства                    отображения схемы
PC

0
1
2
3
4

0
1
2

32
stall_i
stall_i

32
/

2
3
3
5
mem_wd_o
mem_rd_i
wb_data
wb_data
wb_data
32
PC
2
0
2
1
csr_wd
 illegal_instr
CONTROL
STATUS
REGISTERS
WE

clk_i

addr
pc
mcause
rs1_data
rst
imm_data
trap
opcode
read_data
mie
mepc
mtvec
csr_we
csr_op
3
irq
trap
rst_i
csr_wd
mie
RD1
PC
[19:15]
ZE

5
/

32
/

imm_Z

imm_Z

instr_i[31:20]

mret
IRQ
CONTROLLER
exception_i

clk_i

irq_req_i
mie_i
rst_i
irq_cause_o
irq_ret_o
rst_i
trap
mret
irq
irq_ret_o
irq_req_i
mie[16]

imm_Z

csr_wd
irq
trap
mret
mie
irq_req_i
irq_ret_o
jalr
PC
jalr
32
32
32
32
12
32
32
32
32

1

0

stall_i
trap
trap
trap
ill_instr

0

1

ill_instr
32
32
irq
ill_instr
ill_instr
mret_i
irq_o
32'h0000_0002

imm_I

+
RD1
jalr
{[31:1],1'b0}

1

0

1

0

trap
trap
en
rst
\ No newline at end of file diff --git a/.pic/Labs/lab_11_irq_integration/fig_01.drawio.svg b/.pic/Labs/lab_11_irq_integration/fig_01.drawio.svg index f2b3d3f..46ba67c 100644 --- a/.pic/Labs/lab_11_irq_integration/fig_01.drawio.svg +++ b/.pic/Labs/lab_11_irq_integration/fig_01.drawio.svg @@ -1,4 +1,4 @@ -

Main
Decoder

Main...

flag

flag
Register
File
Register...
imm_S
imm_S
imm_U
imm_U
4
4
0
0
RD1
RD1
RD2
RD2
gpr_we
gpr_we
WE
WE

clk_i

clk_i
wb_sel
wb_sel
 mem_size
 mem_size
mem_we
mem_we
alu_op
alu_op
b_sel
b_sel
a_sel
a_sel
jal
jal
b
b
instr
instr
RA1
RA1
RA2
RA2
WA
WA
WD
WD
[19:15]
[19:15]
[24:20]
[24:20]
[11:07]
[11:07]
[31:20]
[31:20]
[31:12], 12'h000
[31:12], 12'h000
[31:25][11:7]
[31:25][11:7]
[31][19:12][20][30:21],1'b0
[31][19:12][20][30:21],1'b0
[31][7][30:25][11:8],1'b0
[31][7][30:25][11:8],1'b0
imm_J
imm_J
imm_B
imm_B
4
4
PC
PC

clk_i

clk_i

rst_i

rst_i
jalr
jalr
ALU
ALU
SE
SE
SE
SE
+
+
mem_wd_o
mem_wd_o
instr_i
instr_i
mem_addr_o
mem_addr_o
instr_addr_o
instr_addr_o
mem_rd_i
mem_rd_i
mem_we_o
mem_we_o
mem_size_o
mem_size_o
instr_addr_o
instr_addr_o

instr_i

instr_i

mem_addr_o

mem_addr_o
mem_we_o
mem_we_o

mem_size_o

mem_size_o

rst_i

rst_i

clk_i

clk_i
SE
SE

0

1

0...

0

1

0...

flag

flag

32
/

32...

32
/

32...

32
/

32...

32
/

32...

32
/

32...

12
/

12...

12
/

12...

21
/

21...

13
/

13...

32
/

32...
mret
mret
SE
SE
mem_req 
mem_req 

mem_req_o

mem_req_o

imm_I

imm_I
— входные сигналы
— входные сигналы
выходные сигналы
— выходные сигналы
mem_req_o
mem_req_o

imm_I

imm_I
RD1
RD1

flag

flag
провода, разорванные        для удобства                    отображения схемы
— провода, разорванные        для удобства...
PC
PC

0
1
2
3
4

0...

0
1
2

0...
32
32
stall_i
stall_i
stall_i
stall_i

32
/

32...
2
2
3
3
3
3
5
5
mem_wd_o
mem_wd_o
mem_rd_i
mem_rd_i
wb_data
wb_data
wb_data
wb_data
wb_data
wb_data
32
32
PC
PC
2
2
0
0
2
2
1
1
csr_wd
csr_wd
 illegal_instr
 illegal_instr
CONTROL
STATUS
REGISTERS
CONTROL...
WE
WE

clk_i

clk_i
addr
addr
pc
pc
mcause
mcause
rs1_data
rs1_data
rst
rst
imm_data
imm_data
trap
trap
opcode
opcode
read_data
read_data
mie
mie
mepc
mepc
mtvec
mtvec
csr_we
csr_we
csr_op
csr_op
3
3
irq
irq
trap
trap
rst_i
rst_i
csr_wd
csr_wd
mie
mie
RD1
RD1
PC
PC
[19:15]
[19:15]
ZE
ZE

5
/

5...

32
/

32...

imm_Z

imm_Z

imm_Z

imm_Z

instr_i[31:20]

instr_i[31:20]
mret
mret
IRQ
CONTROLLER
IRQ...
exception_i
exception_i

clk_i

clk_i
irq_req_i
irq...
mie_i
mie_i
rst_i
rst_i
irq_cause_o
irq_cause...
irq_ret_o
irq_ret_o
rst_i
rst_i
trap
trap
mret
mret
irq
irq
irq_ret_o
irq_ret_o
irq_req_i
irq_req_i
mie[16]
mie[16]

imm_Z

imm_Z
csr_wd
csr_wd
irq
irq
trap
trap
mret
mret
mie
mie
irq_req_i
irq_req_i
irq_ret_o
irq_ret_o
jalr
jalr
PC
PC
jalr
jalr
32
32
32
32
32
32
32
32
12
12
32
32
32
32
32
32
32
32

1

0

1...
stall_i
stall_i
trap
trap
trap
trap
trap
trap
ill_instr
ill_ins...

0

1

0...
ill_instr
ill_ins...
32
32
32
32
irq
irq
ill_instr
ill_ins...
ill_instr
ill_ins...
mret_i
mret_i
irq_o
irq_o
32'h0000_0002
32'h0000_0002

imm_I

imm_I
+
+
RD1
RD1
jalr
jalr
{[31:1],1'b0}
{[31:1],1'b0}

1

0

1...

1

0

1...
trap
trap
trap
trap
en
en
rst
rst
Text is not SVG - cannot display
\ No newline at end of file +

Main
Decoder

flag

Register
File
imm_S
imm_U
4
0
RD1
RD2
gpr_we
WE

clk_i

wb_sel
 mem_size
mem_we
alu_op
b_sel
a_sel
jal
b
instr
RA1
RA2
WA
WD
[19:15]
[24:20]
[11:07]
[31:20]
[31:12], 12'h000
[31:25][11:7]
[31][19:12][20][30:21],1'b0
[31][7][30:25][11:8],1'b0
imm_J
imm_B
4
PC

clk_i

rst_i

jalr
ALU
SE
SE
+
mem_wd_o
instr_i
mem_addr_o
instr_addr_o
mem_rd_i
mem_we_o
mem_size_o
instr_addr_o

instr_i

mem_addr_o

mem_we_o

mem_size_o

rst_i

clk_i

SE

0

1

0

1

flag

32
/

32
/

32
/

32
/

32
/

12
/

12
/

21
/

13
/

32
/

mret
SE
mem_req 

mem_req_o

imm_I

— входные сигналы
выходные сигналы
mem_req_o

imm_I

RD1

flag

провода, разорванные        для удобства                    отображения схемы
PC

0
1
2
3
4

0
1
2

32
stall_i
stall_i

32
/

2
3
3
5
mem_wd_o
mem_rd_i
wb_data
wb_data
wb_data
32
PC
2
0
2
1
csr_wd
 illegal_instr
CONTROL
STATUS
REGISTERS
WE

clk_i

addr
pc
mcause
rs1_data
rst
imm_data
trap
opcode
read_data
mie
mepc
mtvec
csr_we
csr_op
3
irq
trap
rst_i
csr_wd
mie
RD1
PC
[19:15]
ZE

5
/

32
/

imm_Z

imm_Z

instr_i[31:20]

mret
IRQ
CONTROLLER
exception_i

clk_i

irq_req_i
mie_i
rst_i
irq_cause_o
irq_ret_o
rst_i
trap
mret
irq
irq_ret_o
irq_req_i
mie[16]

imm_Z

csr_wd
irq
trap
mret
mie
irq_req_i
irq_ret_o
jalr
PC
jalr
32
32
32
32
12
32
32
32
32

1

0

stall_i
trap
trap
trap
ill_instr

0

1

ill_instr
32
32
irq
ill_instr
ill_instr
mret_i
irq_o
32'h0000_0002

imm_I

+
RD1
jalr
{[31:1],1'b0}

1

0

1

0

trap
trap
en
rst
\ No newline at end of file