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ЛР12. Обновление PS2Receiver.sv

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This commit is contained in:
Andrei Solodovnikov
2023-11-25 19:46:06 +03:00
committed by Andrei Solodovnikov
parent e17599fcd9
commit 8a87549288
1 changed files with 24 additions and 27 deletions
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51
Labs/12. Peripheral units/PS2Receiver.sv
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@@ -1,9 +1,9 @@
module PS2Receiver( module PS2Receiver(
input logic clk, input logic clk_i,
input logic kclk, input logic kclk_i,
input logic kdata, input logic kdata_i,
output logic [15:0] keycodeout, output logic [7:0] keycodeout_o,
output keycode_valid output keycode_valid_o
); );
logic flag; logic flag;
@@ -11,43 +11,40 @@ module PS2Receiver(
logic kclkf, kdataf; logic kclkf, kdataf;
logic [3:0] cnt; logic [3:0] cnt;
assign keycode_valid = flag_shift[0] && !flag_shift[2]; assign keycode_valid_o = flag_shift[0] && !flag_shift[2];
initial begin //for tb initial begin //for tb
cnt = 0; cnt = 0;
keycodeout = 0; keycodeout_o = 0;
flag_shift = 0; flag_shift = 0;
flag = 0; flag = 0;
end end
debouncer debounce( debouncer debounce(
.clk(clk), .clk(clk_i),
.I0(kclk), .I0(kclk_i),
.I1(kdata), .I1(kdata_i),
.O0(kclkf), .O0(kclkf),
.O1(kdataf) .O1(kdataf)
); );
always@(posedge clk) begin always@(posedge clk_i) begin
flag_shift <= (flag_shift << 1) + flag; flag_shift <= (flag_shift << 1) + flag;
end end
always_ff @(negedge(kclkf))begin always_ff @(negedge(kclkf))begin
case(cnt) case(cnt)
0:if(keycodeout != 16'hE000)keycodeout <= 0;//Start bit 0:;
1:keycodeout[0]<=kdataf; 1:keycodeout_o[0]<=kdataf;
2:keycodeout[1]<=kdataf; 2:keycodeout_o[1]<=kdataf;
3:keycodeout[2]<=kdataf; 3:keycodeout_o[2]<=kdataf;
4:keycodeout[3]<=kdataf; 4:keycodeout_o[3]<=kdataf;
5:keycodeout[4]<=kdataf; 5:keycodeout_o[4]<=kdataf;
6:keycodeout[5]<=kdataf; 6:keycodeout_o[5]<=kdataf;
7:keycodeout[6]<=kdataf; 7:keycodeout_o[6]<=kdataf;
8:keycodeout[7]<=kdataf; 8:keycodeout_o[7]<=kdataf;
//TODO ADD PARITY CHECK //TODO ADD PARITY CHECK
9:begin 9:begin
flag<=1'b1; flag<=1'b1;
if(keycodeout[7:0] == 8'hE0) begin
keycodeout <= {keycodeout[7:0], 8'd0};
end
end end
10:flag<=1'b0; 10:flag<=1'b0;
default: cnt <= 0; default: cnt <= 0;
@@ -68,8 +65,8 @@ module debouncer(
); );
logic [4:0]cnt0, cnt1; logic [4:0]cnt0, cnt1;
logi Iv0=0,Iv1=0; logic Iv0=0,Iv1=0;
logi out0, out1; logic out0, out1;
always_ff @(posedge(clk))begin always_ff @(posedge(clk))begin
if (I0==Iv0) begin if (I0==Iv0) begin
@@ -77,7 +74,7 @@ module debouncer(
else cnt0<=cnt0+1; else cnt0<=cnt0+1;
end end
else begin else begin
cnt0<="00000"; cnt0<=5'd0;
Iv0<=I0; Iv0<=I0;
end end
if (I1==Iv1)begin if (I1==Iv1)begin
@@ -85,7 +82,7 @@ module debouncer(
else cnt1<=cnt1+1; else cnt1<=cnt1+1;
end end
else begin else begin
cnt1<="00000"; cnt1<=5'd0;
Iv1<=I1; Iv1<=I1;
end end
end end