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Переработка лабораторных работ, связанных с памятью (#89)
* Переработка лабораторных работ, связанных с памятью Существенно переработаны ЛР3 и ЛР7: Из ЛР3 убрано задание реализовать память данных. Эта память использовалась только студентами ИВТ и только в рамках одной лабы. В итоге использовалась готовая память, и ничего не мешает использовать ее с самого начала. Задание по реализации памяти инструкций также претерпело изменения. Теперь код памяти инструкций предоставляется сразу. Это объясняется тем, что код модуля состоит в общем-то из 4х строк, на которые тратится слишком много времени (с учетом добавления тестбенча и проверок). Кроме того, использование готового кода позволяет дать модуль чуть посложнее (с параметризацией размера). По итогу правок, третья лабораторная работа превращается чисто в лабораторную по написанию регистрового файла, что должно положительно сказаться на кривой сложности лаб. После второй лабы происходит слишком резкий скачок в объемах работы. Соответственно, в связи с тем, что память данных больше не делается на третьей лабе, дополнительная ЛР по памяти данных с byte enable необходимо перенести до реализации тракта данных. * ЛР3, 5, 6. Правки из ревью * ЛР7. Добавление иллюстраций
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Andrei Solodovnikov
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Labs/07. Datapath/board files/nexys_riscv_unit.sv
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334
Labs/07. Datapath/board files/nexys_riscv_unit.sv
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/* -----------------------------------------------------------------------------
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* Project Name : Architectures of Processor Systems (APS) lab work
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* Organization : National Research University of Electronic Technology (MIET)
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* Department : Institute of Microdevices and Control Systems
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* Author(s) : Alexander Kharlamov
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* Email(s) : sasha_xarlamov@org.miet.ru
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See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details.
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* ------------------------------------------------------------------------------
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*/
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typedef enum {
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INSTR_ALU , // branch and computational
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INSTR_LI , // const load
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INSTR_IN , // periphery load
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INSTR_JUMP ,
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INSTR_NOP // ws == 3
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} Instruction_type;
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typedef enum {
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CH_0 = 0,
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CH_1,
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CH_2,
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CH_3,
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CH_4,
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CH_5,
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CH_6,
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CH_7,
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CH_8,
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CH_9,
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CH_A,
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CH_b,
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CH_c,
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CH_d,
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CH_E,
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CH_F,
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CH_G,
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CH_L,
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CH_n,
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CH_o,
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CH_r,
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CH_S,
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CH_t,
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CH_u,
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CH_X,
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CH_P,
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CH_J,
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CH_q,
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CH_i,
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CH_m,
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CH_y,
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CH_h,
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CH_SPACE
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} Char;
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typedef struct {
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logic ca;
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logic cb;
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logic cc;
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logic cd;
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logic ce;
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logic cf;
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logic cg;
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logic dp;
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} Semseg;
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module nexys_riscv_unit(
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input logic clk_i,
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input logic arstn_i,
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input logic btnd_i,
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output logic ca_o,
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output logic cb_o,
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output logic cc_o,
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output logic cd_o,
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output logic ce_o,
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output logic cf_o,
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output logic cg_o,
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output logic dp_o,
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output logic [ 7:0] an_o
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);
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logic btnd_sync;
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sync sync (
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.clk_i ,
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.data_i (btnd_i ),
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.data_o (btnd_sync)
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);
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logic btnd_debounce;
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debounce debounce (
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.clk_i ,
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.arstn_i (1'b1 ),
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.data_i (btnd_sync ),
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.data_o (btnd_debounce)
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);
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logic bufg_clk;
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BUFG dut_bufg(
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.I (btnd_debounce),
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.O (bufg_clk )
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);
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riscv_unit unit(
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.clk_i (bufg_clk),
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.rst_i (!arstn_i)
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);
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logic [31:0] instr_addr;
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logic [31:0] instr;
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assign instr_addr = unit.core.instr_addr_o;
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assign instr = unit.core.instr_i;
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import alu_opcodes_pkg::*;
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logic illegal_instr;
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logic [6:0] opcode;
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assign opcode = instr[6:0];
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Char op_chars[0:3];
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import decoder_pkg::*;
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always_comb begin
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op_chars = '{4{CH_SPACE}};
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case (opcode)
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{LOAD_OPCODE , 2'b11}: op_chars = '{CH_L, CH_o, CH_A, CH_d};
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{MISC_MEM_OPCODE, 2'b11}: op_chars = '{CH_m, CH_i, CH_S, CH_c};
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{OP_IMM_OPCODE , 2'b11}: op_chars = '{CH_o, CH_P, CH_i, CH_m};
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{AUIPC_OPCODE , 2'b11}: op_chars = '{CH_A, CH_u, CH_i, CH_P};
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{STORE_OPCODE , 2'b11}: op_chars = '{CH_S, CH_t, CH_o, CH_r};
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{OP_OPCODE , 2'b11}: op_chars[0:1] = '{CH_o, CH_P};
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{LUI_OPCODE , 2'b11}: op_chars[0:2] = '{CH_L, CH_u, CH_i};
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{BRANCH_OPCODE , 2'b11}: op_chars = '{CH_b, CH_r, CH_c, CH_h};
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{JALR_OPCODE , 2'b11}: op_chars = '{CH_J, CH_A, CH_L, CH_r};
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{JAL_OPCODE , 2'b11}: op_chars[0:2] = '{CH_J, CH_A, CH_L};
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{SYSTEM_OPCODE , 2'b11}: op_chars[0:2] = '{CH_S, CH_y, CH_S};
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default : op_chars[0:2] = '{CH_i, CH_L, CH_L};
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endcase
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end
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Char all_chars[0:7];
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assign all_chars[0:3] = {
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Char'(instr_addr[15:12]),
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Char'(instr_addr[11: 8]),
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Char'(instr_addr[ 7: 4]),
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Char'(instr_addr[ 3: 0])
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};
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assign all_chars[4:7] = op_chars;
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Char current_char;
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logic [7:0] an;
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semseg_one2many #(
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.DATA_T (Char)
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) semseg_one2many (
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.clk100m_i (clk_i ),
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.arstn_i (arstn_i ),
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.all_semsegs_i (all_chars ),
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.current_semseg_o (current_char),
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.an_o (an )
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);
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Semseg current_semseg;
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char2semseg char2semseg (
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.char_i (current_char ),
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.semseg_o (current_semseg)
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);
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assign ca_o = current_semseg.ca;
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assign cb_o = current_semseg.cb;
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assign cc_o = current_semseg.cc;
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assign cd_o = current_semseg.cd;
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assign ce_o = current_semseg.ce;
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assign cf_o = current_semseg.cf;
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assign cg_o = current_semseg.cg;
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assign dp_o = current_semseg.dp;
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assign an_o = an;
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endmodule
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module char2semseg #(
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parameter bit HEX_ONLY = 1'b0
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) (
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input Char char_i,
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output Semseg semseg_o
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);
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localparam bit [6:0] BLANK = '1;
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logic [6:0] semseg;
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always_comb begin
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case (char_i)
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CH_0 : semseg = ~7'h3F;
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CH_1 : semseg = ~7'h06;
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CH_2 : semseg = ~7'h5B;
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CH_3 : semseg = ~7'h4F;
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CH_4 : semseg = ~7'h66;
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CH_5 : semseg = ~7'h6D;
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CH_6 : semseg = ~7'h7D;
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CH_7 : semseg = ~7'h07;
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CH_8 : semseg = ~7'h7F;
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CH_9 : semseg = ~7'h6F;
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CH_A : semseg = ~7'h5F;
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CH_b : semseg = ~7'h7C;
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CH_c : semseg = ~7'h58;
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CH_d : semseg = ~7'h5E;
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CH_E : semseg = ~7'h79;
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CH_F : semseg = ~7'h71;
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CH_G : semseg = ~7'h3D;
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CH_L : semseg = ~7'h38;
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CH_n : semseg = ~7'h54;
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CH_o : semseg = ~7'h5C;
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CH_r : semseg = ~7'h50;
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CH_S : semseg = ~7'h64;
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CH_t : semseg = ~7'h78;
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CH_u : semseg = ~7'h1C;
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CH_X : semseg = ~7'h76;
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CH_P : semseg = ~7'h73;
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CH_J : semseg = ~7'h1E;
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CH_q : semseg = ~7'h67;
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CH_i : semseg = ~7'h30;
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CH_m : semseg = ~7'h77;
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CH_y : semseg = ~7'h6E;
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CH_h : semseg = ~7'h74;
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default : semseg = BLANK;
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endcase
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end
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assign semseg_o.ca = semseg[0];
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assign semseg_o.cb = semseg[1];
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assign semseg_o.cc = semseg[2];
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assign semseg_o.cd = semseg[3];
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assign semseg_o.ce = semseg[4];
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assign semseg_o.cf = semseg[5];
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assign semseg_o.cg = semseg[6];
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assign semseg_o.dp = 1'b1;
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endmodule
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module semseg_one2many #(
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parameter int unsigned SEMSEGS_NUM = 8,
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parameter type DATA_T
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) (
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input DATA_T all_semsegs_i[0:SEMSEGS_NUM-1],
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input logic clk100m_i,
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input logic arstn_i,
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output DATA_T current_semseg_o,
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output logic [7:0] an_o
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);
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logic clk_i;
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assign clk_i = clk100m_i;
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localparam int COUNTER_WIDTH = 10;
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logic [COUNTER_WIDTH-1:0] counter_next;
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logic [COUNTER_WIDTH-1:0] counter_ff;
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assign counter_next = counter_ff + COUNTER_WIDTH'('b1);
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) counter_ff <= '0;
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else counter_ff <= counter_next;
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end
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logic [7:0] an_ff;
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logic [7:0] an_next;
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logic an_en;
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assign an_next = {an_ff[$left(an_ff)-1:0], an_ff[$left(an_ff)]};
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assign an_en = ~|counter_ff;
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) an_ff <= ~8'b1;
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else if (an_en) an_ff <= an_next;
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end
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DATA_T current_semseg;
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always_comb begin
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unique case (1'b0)
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an_ff[0]: current_semseg = all_semsegs_i[7];
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an_ff[1]: current_semseg = all_semsegs_i[6];
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an_ff[2]: current_semseg = all_semsegs_i[5];
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an_ff[3]: current_semseg = all_semsegs_i[4];
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an_ff[4]: current_semseg = all_semsegs_i[3];
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an_ff[5]: current_semseg = all_semsegs_i[2];
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an_ff[6]: current_semseg = all_semsegs_i[1];
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an_ff[7]: current_semseg = all_semsegs_i[0];
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endcase
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end
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assign current_semseg_o = current_semseg;
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assign an_o = an_ff;
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endmodule
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module debounce #(
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parameter int unsigned MAX_COUNT = 10000
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) (
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input logic clk_i,
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input logic arstn_i,
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input logic data_i,
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output logic data_o
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);
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localparam int COUNTER_WIDTH = $clog2(MAX_COUNT);
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logic [COUNTER_WIDTH-1:0] counter_next;
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logic [COUNTER_WIDTH-1:0] counter_ff;
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assign counter_next = (data_o != data_i) ? counter_ff - COUNTER_WIDTH'('b1) :
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COUNTER_WIDTH'(MAX_COUNT);
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) counter_ff <= COUNTER_WIDTH'(MAX_COUNT);
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else counter_ff <= counter_next;
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end
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always_ff @(posedge clk_i or negedge arstn_i) begin
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if (!arstn_i) data_o <= '0;
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else if (~|counter_ff) data_o <= data_i;
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end
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endmodule
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module sync #(
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parameter int unsigned SYNC_STAGES = 3
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) (
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input logic clk_i,
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input logic data_i,
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output logic data_o
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);
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logic [SYNC_STAGES-1:0] sync_buffer_ff;
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logic [SYNC_STAGES-1:0] sync_buffer_next;
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assign sync_buffer_next = {sync_buffer_ff[$left(sync_buffer_ff)-1:0], data_i};
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always_ff @(posedge clk_i) begin
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sync_buffer_ff <= sync_buffer_next;
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end
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assign data_o = sync_buffer_ff[$left(sync_buffer_ff)];
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endmodule
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