From e6b58feb4bc9fa8bfa7f0e4d6dc7eca99c5f1b11 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 12 Mar 2024 13:33:46 +0300 Subject: [PATCH 01/32] =?UTF-8?q?=D0=9B=D0=A03.=20=D0=94=D0=BE=D0=B1=D0=B0?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D1=82=D0=B5=D1=81=D1=82?= =?UTF-8?q?=D0=BE=D0=B2=D0=BE=D0=B3=D0=BE=20=D1=81=D1=86=D0=B5=D0=BD=D0=B0?= =?UTF-8?q?=D1=80=D0=B8=D1=8F=20=D0=B4=D0=BB=D1=8F=20=D1=80=D0=B5=D0=B3?= =?UTF-8?q?=D0=B8=D1=81=D1=82=D1=80=D0=BE=D0=B2=D0=BE=D0=B3=D0=BE=20=D1=84?= =?UTF-8?q?=D0=B0=D0=B9=D0=BB=D0=B0?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit В тестбенче был пропущен кейс на чтение из нулевого регистра до какой-либо записи в регистровый файл из-за чего не обнаруживалась ошибка, когда нулевой регистр принимал значение 0 только в случае записи любого значения по адресу ноль. Closes #21. --- Labs/03. Register file and memory/tb_rf_riscv.sv | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Labs/03. Register file and memory/tb_rf_riscv.sv b/Labs/03. Register file and memory/tb_rf_riscv.sv index 9662494..b545493 100644 --- a/Labs/03. Register file and memory/tb_rf_riscv.sv +++ b/Labs/03. Register file and memory/tb_rf_riscv.sv @@ -74,6 +74,17 @@ module tb_rf_riscv(); $display("invalid memory size"); err_count = err_count + 1; end + RA1 <= 'b0; + RA2 <= 'b0; + @(posedge CLK); + if( RD1 !== 'b0 ) begin + $display("time = %0t. invalid data when reading at address 0: RD1 = %h", $time, RD1); + err_count = err_count + 1; + end + if( RD2 !== 'b0 ) begin + $display("time = %0t. invalid data when reading at address 0: RD2 = %h", $time, RD2); + err_count = err_count + 1; + end @(posedge CLK); WD <= 32'd1; WA <= '0; From 9c011077bb23b71ce3649dec34b37769a47ebfc8 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 12 Mar 2024 13:49:15 +0300 Subject: [PATCH 02/32] =?UTF-8?q?=D0=9B=D0=A03.=20=D0=9E=D0=B1=D0=BD=D0=BE?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D1=83=D0=BA=D0=B0=D0=B7?= =?UTF-8?q?=D0=B0=D0=BD=D0=B8=D1=8F=20=D0=BF=D0=BE=20=D1=80=D0=B5=D0=B0?= =?UTF-8?q?=D0=BB=D0=B8=D0=B7=D0=B0=D1=86=D0=B8=D0=B8=20=D0=BF=D0=B0=D0=BC?= =?UTF-8?q?=D1=8F=D1=82=D0=B8=20=D0=B4=D0=B0=D0=BD=D0=BD=D1=8B=D1=85?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Добавлено примечание о количестве ячеек памяти данных. --- Labs/03. Register file and memory/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Labs/03. Register file and memory/README.md b/Labs/03. Register file and memory/README.md index 13f100e..f61591e 100644 --- a/Labs/03. Register file and memory/README.md +++ b/Labs/03. Register file and memory/README.md @@ -322,7 +322,7 @@ mоdulе rf_r𝚒sсv( 3. Реализуйте память данных. Для этого: 1. В `Design Sources` проекта создайте `SystemVerilog`-файл `data_mem.sv`. 2. Опишите в нем модуль памяти данных с таким же именем и портами, как указано в задании. - 1. Описание модуля будет схожим с описанием модуля памяти инструкций, однако порт чтения в этот раз будет **синхронным** (запись в него будет происходить в блоке `always_ff`). Кроме того, необходимо будет описать логику записи данных в память. + 1. Описание модуля будет схожим с описанием модуля памяти инструкций, однако порт чтения в этот раз будет **синхронным** (запись в него будет происходить в блоке `always_ff`). Количество ячеек в памяти данных — 4096. Кроме того, необходимо будет описать логику записи данных в память. 2. Запись в ячейки памяти описывается подобно записи данных в [регистры](../../Basic%20Verilog%20structures/Registers.md), только при этом, происходит доступ к конкретной ячейке памяти с помощью входа `addr_i` (как осуществляется доступ к ячейкам памяти сказано в разделе [описание памяти на языке SystemVerilog](#описание-памяти-на-языке-systemverilog)). 3. Доступ к ячейкам (на запись и чтение) осуществляется по адресу `addr_i[13:2]`. 4. Обратите внимание что работа с памятью должна осуществляться только когда сигнал `mem_req_i == 1`, в противном случае запись не должна производиться, а на шине `read_data_o` должен оставаться результат предыдущего чтения. From d844f396ae5f3980ee7440cafe0cd8b46b11a766 Mon Sep 17 00:00:00 2001 From: BROsandr <53278658+BROsandr@users.noreply.github.com> Date: Fri, 15 Mar 2024 11:42:33 +0300 Subject: [PATCH 03/32] =?UTF-8?q?=D0=9B=D0=A04.=20=D0=98=D1=81=D0=BF=D1=80?= =?UTF-8?q?-=D0=B8=D0=B5=20=D0=BF=D0=B0=D1=82=D1=82=D0=B5=D1=80=D0=BD?= =?UTF-8?q?=D0=B0=20jump'=D0=B0=20(#71)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/04. Primitive programmable device/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Labs/04. Primitive programmable device/README.md b/Labs/04. Primitive programmable device/README.md index bd4cae8..8b33479 100644 --- a/Labs/04. Primitive programmable device/README.md +++ b/Labs/04. Primitive programmable device/README.md @@ -258,7 +258,7 @@ _Рисунок 5. Реализация безусловного переход 1. 10 вычислительных инструкций `0 0 01 alu_op RA1 RA2 xxxx xxxx WA` 2. Инструкция загрузки константы `0 0 00 const WA` 3. Инструкция загрузки из внешних устройств `0 0 10 xxx xxxx xxxx xxxx xxxx xxxx WA` -4. Безусловный переход `1 0 xx xxx xxxx xxxx xxxx const xxxxx` +4. Безусловный переход `1 x xx xxx xxxx xxxx xxxx const xxxxx` 5. 6 инструкций условного перехода `0 1 xx alu_op RA1 RA2 const x xxxx` При кодировании инструкций используются следующие поля: From ff6f2187913238749b5e1db1859822ba5cbdad17 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Sat, 16 Mar 2024 22:55:27 +0300 Subject: [PATCH 04/32] Update lab_03.data_mem.sv MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Ошибка в отбрасывании бит адреса --- Labs/Made-up modules/lab_03.data_mem.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Labs/Made-up modules/lab_03.data_mem.sv b/Labs/Made-up modules/lab_03.data_mem.sv index 45829d5..ba94f01 100644 --- a/Labs/Made-up modules/lab_03.data_mem.sv +++ b/Labs/Made-up modules/lab_03.data_mem.sv @@ -24,7 +24,7 @@ module data_mem ( logic [31:0] RAM [0:4095]; logic [31:0] addr; -assign addr = {2'b0, addr_i[31:2]}; +assign addr = {20'b0, addr_i[13:2]}; always_ff @(posedge clk_i) begin if(write_enable_i&mem_req_i) RAM[addr[13'o10+13'b101:'hBA & 'h45]][{5{1'b1}}:{3'd7,2'b00}] <= write_data_i['h1f:'h1c]; From b24c302dfac0944c46fca6fa2aef28986bbcb92c Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Mon, 18 Mar 2024 13:02:32 +0300 Subject: [PATCH 05/32] =?UTF-8?q?=D0=9F=D1=80=D0=B8=D0=BC=D0=B5=D0=BD?= =?UTF-8?q?=D0=B5=D0=BD=D0=B8=D0=B5=20=D1=81=D1=82=D0=B8=D0=BB=D0=B8=D1=81?= =?UTF-8?q?=D1=82=D0=B8=D1=87=D0=B5=D1=81=D0=BA=D0=B8=D1=85=20=D0=BF=D1=80?= =?UTF-8?q?=D0=B0=D0=B2=D0=BE=D0=BA=20=D0=BF=D0=BE=D1=81=D0=BB=D0=B5=20?= =?UTF-8?q?=D0=B2=D1=8B=D1=87=D0=B8=D1=82=D0=BA=D0=B8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .github/Intro.md | 10 +++++----- Introduction/How FPGA works.md | 8 ++++---- Introduction/Implementation steps.md | 2 +- Introduction/README.md | 2 +- Introduction/What is HDL.md | 2 +- Labs/01. Adder/README.md | 4 ++-- README.md | 4 ++-- 7 files changed, 16 insertions(+), 16 deletions(-) diff --git a/.github/Intro.md b/.github/Intro.md index ba00401..a86f226 100644 --- a/.github/Intro.md +++ b/.github/Intro.md @@ -76,21 +76,21 @@ Вне зависимости от вашего уровня подготовки, работу с этим курсом рекомендуется начать с прочтения документов из части: "Введение". -Далее можно приступать к разделу "Лабораторные работы". Перед каждым лабораторным занятием вам **рекомендуется** ознакомиться с методичкой, они очень подробные и их чтение требует какого-то времени. Время отведенное на лабораторное занятие рекомендуется использовать по-максимуму, то есть заниматься практической деятельностью, консультироваться с преподавателем, отлаживать разработанные блоки устройства и тому подобное, а для этого лучше прочитать методичку заранее. +Далее можно приступать к разделу "Лабораторные работы". Перед каждым лабораторным занятием вам **рекомендуется** ознакомиться с методичкой, они очень подробные и их чтение требует какого-то времени. Время, отведенное на лабораторное, занятие рекомендуется использовать по-максимуму, то есть заниматься практической деятельностью, консультироваться с преподавателем, отлаживать разработанные блоки устройства и тому подобное, а для этого лучше прочитать методичку заранее. Кроме того, важно отметить, что в начале каждой методички размещен раздел "Допуск", где перечислены все материалы со ссылками на главы раздела "Базовые конструкции SystemVerilog", которые студент **должен освоить** перед выполнением этой лабораторной работы. Данный раздел ориентирован в первую очередь на студентов, не работавших ранее с Verilog/SystemVerilog, однако, даже если вы работали с этими языками, рекомендуется пролистать данные главы и проверить свои знания в разделе "Проверь себя". -Традиционно, данные лабораторные считаются сложными. Однако за годы отработки методичек со студентами, было написано множество вспомогательных материалов, уточнений, а так же акцентов на места, которые могут привести к ошибке. В данный момент, для успешного выполнения лабораторной работы от студента требуется только внимательно прочитать предоставленный ему материал и не бояться задать вопрос, если что-то непонятно. +Традиционно, данные лабораторные считаются сложными. Однако за годы отработки методичек со студентами, было написано множество вспомогательных материалов, уточнений, а также акцентов на места, которые могут привести к ошибке. В данный момент, для успешного выполнения лабораторной работы от студента требуется только внимательно прочитать предоставленный ему материал и не бояться задать вопрос, если что-то непонятно. Лабораторные занятия будут проходить с использованием САПР `Vivado` (и отладочными стендами `Nexys A7`). Это очень сложный профессиональный инструмент, на полноценное изучение которого могут уйти годы. Во время данного курса лабораторных работ нет времени на эти годы, поэтому для вас собрана основная информация по взаимодействию с САПР в разделе "Основы Vivado". Этой информации хватит, чтобы с помощью `Vivado` реализовать весь цикл лабораторных работ. -Если вы читаете данную книгу не в рамках курса АПС, вы вольны в выборе как программных средств, так и способов отладки. [Репозиторий](https://github.com/MPSU/APS), сопровождающий эту книгу будет содержать некоторые файлы, специализированные для плат Nexys A7 (так называемые _ограничения_/_констрейны_), однако при должном уровне навыков вы с легкостью сможете портировать его под свою плату. В этому случае, авторы будут признательны, если вы предоставите получившиеся файлы и название платы, чтобы их можно было добавить в отдельную папку по другим платам для будущих читателей. По всем вопросам/замечаниям/предложениям вы можете связаться с авторами курса через механику `Issues` и `Discussions` данного репозитория. +Если вы читаете данную книгу не в рамках курса АПС, вы вольны в выборе как программных средств, так и способов отладки. [Репозиторий](https://github.com/MPSU/APS), сопровождающий эту книгу будет содержать некоторые файлы, специализированные для плат Nexys A7 (так называемые _ограничения_/_констрейны_), однако при должном уровне навыков вы с легкостью сможете портировать его под свою плату. В этому случае, авторы будут признательны, если вы предоставите получившиеся файлы и название платы, чтобы их можно было добавить в отдельную папку по другим платам для будущих читателей. По всем вопросам/замечаниям/предложениям вы можете связаться с авторами курса через разделы `Issues` и `Discussions` данного репозитория. Эта книга может быть интересна и полезна читателю, не имеющему никакой отладочной платы: проверка работоспособности осуществляется в первую очередь на моделировании, т.е. программно (на самом деле, 90% времени вы будете проверять все именно посредством моделирования). -В ходе выполнения лабораторных работ вы наверняка столкнетесь как с ошибками связанными с работой Vivado, так и с ошибками описания на языке SystemVerilog. В первую очередь, рекомендуется ознакомиться с текстом ошибки. В случае ошибок, связанных с языком SystemVerilog, чаще всего там содержится вся необходимая информация по её устранению. В случае, если текст непонятен, рекомендуется ознакомиться со [списком типичных ошибок](Other/FAQ.md). +В ходе выполнения лабораторных работ вы наверняка столкнетесь как с ошибками, связанными с работой Vivado, так и с ошибками описания на языке SystemVerilog. В первую очередь, рекомендуется ознакомиться с текстом ошибки. В случае ошибок, связанных с языком SystemVerilog, чаще всего там содержится вся необходимая информация по её устранению. В случае, если текст непонятен, рекомендуется ознакомиться со [списком типичных ошибок](Other/FAQ.md). -Материал этой книги будет пестрить множеством ссылок, которые в электронной версии этой книги, разумеется, будут кликабельными. Однако, если вы имеете удовольствие читать эту книгу в "аналоговом" формате, для вашего удобства все ссылки будут представлены в виде сносок под соответствующей страницей в текстовом формате. Текстовый формат вместо QR-кодов выбран чтобы иметь возможность вбить ссылку вручную на компьютере (все ссылки будут представлены в формате Unicode, так что не беспокойтесь, что вам придется вводить что-то наподобие "https://ru.wikipedia.org/wiki/%D0%A2%D1%80%D0%B8%D0%B3%D0%B3%D0%B5%D1%80"). Кроме того, "умные" камеры современных смартфонов отлично справляются с распознаванием текстовых ссылок, поэтому авторы надеются что и с этой стороны отсутствие QR-кодов не произведет неудобств. +Материал этой книги будет пестрить множеством ссылок, которые в электронной версии этой книги, разумеется, будут кликабельными. Однако, если вы имеете удовольствие читать эту книгу в "аналоговом" формате, для вашего удобства все ссылки будут представлены в виде сносок под соответствующей страницей в текстовом формате. Текстовый формат вместо QR-кодов выбран чтобы иметь возможность вбить ссылку вручную на компьютере (все ссылки будут представлены в формате Unicode, так что не беспокойтесь, что вам придется вводить что-то наподобие "https://ru.wikipedia.org/wiki/%D0%A2%D1%80%D0%B8%D0%B3%D0%B3%D0%B5%D1%80"). Кроме того, "умные" камеры современных смартфонов отлично справляются с распознаванием текстовых ссылок, поэтому авторы надеются, что и с этой стороны отсутствие QR-кодов не произведет неудобств. Большая часть информации, касающаяся архитектуры RISC-V взята напрямую из спецификации. Поскольку работа над спецификацией все ещё идёт (хотя базовый набор инструкций rv32i уже заморожен и не изменится), чтобы ссылки на конкретные страницы спецификации имели смысл, они будут даваться на следующие версии двух документов: diff --git a/Introduction/How FPGA works.md b/Introduction/How FPGA works.md index 284a623..25186e0 100644 --- a/Introduction/How FPGA works.md +++ b/Introduction/How FPGA works.md @@ -17,7 +17,7 @@ ## История появления ПЛИС -До появления интегральных схем, электронные схемы собирались из отдельных элементов, как модель, собранная из кубиков Lego. В случае, если при сборке электронной схемы была допущена ошибка, вы могли исправить её ручной корректировкой соединения элементов подобно исправлению ошибки, допущенной при сборке модели Lego. +До появления интегральных схем электронные схемы собирались из отдельных элементов, как модель, собранная из кубиков Lego. В случае, если при сборке электронной схемы была допущена ошибка, вы могли исправить её ручной корректировкой соединения элементов подобно исправлению ошибки, допущенной при сборке модели Lego. С улучшением технологических процессов произошла миниатюризация базовых элементов, из которых состоят электронные схемы, что привело к появлению интегральных схем — электронных схем, выполненных на полупроводниковой подложке и заключенных в неразборный корпус. В большинстве случаев, исправить ошибку, допущенную при разработке и изготовлении интегральной схемы становится невозможным. С учетом того, что изготовление прототипа интегральной схемы является затратным мероприятием (от десятков тысяч до миллионов долларов в зависимости от тех процесса и площади изготавливаемого кристалла), возникла необходимость в способе проверки прототипа схемы до изготовления её прототипа. Так появились **программируемые логические интегральные схемы** (**ПЛИС**). ПЛИС содержит некое конечное множество базовых блоков (примитивов), программируемые блоки межсоединений примитивов и блоки ввода-вывода. Подав определенный набор воздействий на ПЛИС (**запрограммировав** её), можно настроить примитивы, их межсоединения между собой и блоками ввода-вывода, чтобы получить определенную цифровую схему. Удобство ПЛИС заключается в том, что в случае обнаружения ошибки на прототипе, исполненном в ПЛИС, вы можете исправить свою цифровую схему, и повторно запрограммировать ПЛИС. @@ -41,19 +41,19 @@ Существует множество логических вентилей, но чаще всего используется четыре из них: **И**, **ИЛИ**, **Исключающее ИЛИ**, **НЕ**. Каждый из этих элементов принимает на вход **цифровое значение** (см. [**цифровая схема**](#цифровые-схемы)), выполняет определенную **логическую функцию** над входами и подает на выход результат этой функции в виде **цифрового значения**. -Логический вентиль **И** принимает два входа и выдает на выход значение `1` только в том случае, если оба входа равны `1`. Если хотя бы один из входов `0`, то на выходе будет `0`. На схемах, логический вентиль **И** отображается следующим образом: +Логический вентиль **И** принимает два входа и выдает на выход значение `1` только в том случае, если оба входа равны `1`. Если хотя бы один из входов `0`, то на выходе будет `0`. На схемах логический вентиль **И** отображается следующим образом: ![../.pic/Introduction/How%20FPGA%20works/fig_01.drawio.svg](../.pic/Introduction/How%20FPGA%20works/fig_01.drawio.svg) _Рисунок 1. Обозначение логического вентиля **И**._ -Логический вентиль **ИЛИ** принимает два входа и выдает на выход значение `1` в случае, если хотя бы один из входов равен `1`. Если оба входа равны `0`, то на выходе будет `0`. На схемах, логический вентиль **ИЛИ** отображается следующим образом: +Логический вентиль **ИЛИ** принимает два входа и выдает на выход значение `1` в случае, если хотя бы один из входов равен `1`. Если оба входа равны `0`, то на выходе будет `0`. На схемах логический вентиль **ИЛИ** отображается следующим образом: ![../.pic/Introduction/How%20FPGA%20works/fig_02.drawio.svg](../.pic/Introduction/How%20FPGA%20works/fig_02.drawio.svg) _Рисунок 2. Обозначение логического вентиля **ИЛИ**._ -Логический вентиль **Исключающее ИЛИ** принимает два входа и выдает на выход значение `1` в случае, если значения входов не равны между собой (один из них равен `1`, а другой `0`). Если значения входов равны между собой (оба равны `0` или оба равны `1`), то на выходе будет `0`. На схемах, логический вентиль **Исключающее ИЛИ** отображается следующим образом: +Логический вентиль **Исключающее ИЛИ** принимает два входа и выдает на выход значение `1` в случае, если значения входов не равны между собой (один из них равен `1`, а другой `0`). Если значения входов равны между собой (оба равны `0` или оба равны `1`), то на выходе будет `0`. На схемах логический вентиль **Исключающее ИЛИ** отображается следующим образом: ![../.pic/Introduction/How%20FPGA%20works/fig_03.drawio.svg](../.pic/Introduction/How%20FPGA%20works/fig_03.drawio.svg) diff --git a/Introduction/Implementation steps.md b/Introduction/Implementation steps.md index 64dba2f..15f250d 100644 --- a/Introduction/Implementation steps.md +++ b/Introduction/Implementation steps.md @@ -200,7 +200,7 @@ set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { resetn ![cell_add../.pic/Introduction/Implementation%20steps/fig_04.png](../.pic/Introduction/Implementation%20steps/fig_04.png) -Теперь, мы можем посмотреть на "внутренности" нашей ПЛИС `xc7a100tcsg324-1` и то, как через её примитивы будет реализована наша схема. Для этого, необходимо отрыть имплементированное устройство: `Implementation -> Open implemented design`. Откроется следующее окно: +Теперь, мы можем посмотреть на "внутренности" нашей ПЛИС `xc7a100tcsg324-1` и то, как через её примитивы будет реализована наша схема. Для этого необходимо отрыть имплементированное устройство: `Implementation -> Open implemented design`. Откроется следующее окно: ![../.pic/Introduction/Implementation%20steps/fig_05.png](../.pic/Introduction/Implementation%20steps/fig_05.png) diff --git a/Introduction/README.md b/Introduction/README.md index 44f3409..06aecbc 100644 --- a/Introduction/README.md +++ b/Introduction/README.md @@ -10,6 +10,6 @@ И в довершение, вам предлагается прочитать документ "[Implementation Steps](./Implementation%20steps.md)". Этот документ дополнит ваше понимание о принципе работы ПЛИС и позволит посмотреть на некоторые её реальные элементы изнутри. -Обратите внимание, что во втором абзаце не было использовано слово "поймете". Часто это слово несет не тот смысл. Можно прочесть документ и **понять** каждое его слово, но не постигнуть смысла, который в этих слова лежал (**слышать**, но не **слушать**). В романе Роберта Хайнлайна "_Чужак в чужой стране_" вводится особое марсианское слово, непереводимое на земной язык: "**грокать**", которое имеет множество значений. В первом приближении можно подумать, что это слово переводится как "понять", однако это не так. Например, на Марсе очень мало воды и процесс её питья марсианами (по сюжету романа, разумеется) является целым ритуалом, и обозначается этим же словом "грокать". Грокать что-то — означает что это что-то стало частью твоего естества. В отношении информации это означает, это информация стала частью тебя, изменила то как ты думаешь. Грокать — это постичь что-то на самом глубинном уровне, это видеть девушку в красном сквозь завесу падающих зеленых символов. Даже этот абзац расписан для того, чтобы вы не просто поняли что эти документы важно понять — а грокнули то, что эти документы важно грокнуть. +Обратите внимание, что во втором абзаце не было использовано слово "поймете". Часто это слово несет не тот смысл. Можно прочесть документ и **понять** каждое его слово, но не постигнуть смысла, который в этих слова лежал (**слышать**, но не **слушать**). В романе Роберта Хайнлайна "_Чужак в чужой стране_" вводится особое марсианское слово, непереводимое на земной язык: "**грокать**", которое имеет множество значений. В первом приближении можно подумать, что это слово переводится как "понять", однако это не так. Например, на Марсе очень мало воды и процесс её питья марсианами (по сюжету романа, разумеется) является целым ритуалом, и обозначается этим же словом "грокать". Грокать что-то — означает что это что-то стало частью твоего естества. В отношении информации это означает, это информация стала частью тебя, изменила то, как ты думаешь. Грокать — это постичь что-то на самом глубинном уровне, это видеть девушку в красном сквозь завесу падающих зеленых символов. Даже этот абзац расписан для того, чтобы вы не просто поняли, что эти документы важно понять — а грокнули то, что эти документы важно грокнуть. На самом деле не важно, каким словом будет обозначен результат вашего прочтения. Важно то, что если после того как вы прочтете эти документы, на лабах вы будете употреблять словосочетания наподобие: "_объявляем переменную_", значит что-то пошло не так, и образ вашего мышления все еще заперт в парадигме "программирования". Это не то чтобы плохо, просто усложнит вам процесс изучения и выполнения лабораторных работ. diff --git a/Introduction/What is HDL.md b/Introduction/What is HDL.md index dd2fd1d..e0bb401 100644 --- a/Introduction/What is HDL.md +++ b/Introduction/What is HDL.md @@ -28,7 +28,7 @@ _Рисунок 3. Структурная схема intel 4004[[2]](https://en. _Рисунок 4. Структурная схема блока аппаратного шифрования по алгоритму AES[[3]](https://iis-people.ee.ethz.ch/~kgf/acacia/acacia_thesis.pdf)._ Заметьте, что даже этот блок не является атомарным. Каждая операция Исключающего ИЛИ, умножения, мультиплексирования сигнала и таблицы подстановки — это отдельные блоки, функционал которых еще надо реализовать. -В какой-то момент, инженеры поняли, что проще описать цифровую схему в текстовом представлении, нежели в графическом. +В какой-то момент инженеры поняли, что проще описать цифровую схему в текстовом представлении, нежели в графическом. Как можно описать цифровую схему текстом? Рассмотрим цифровую схему полусумматора: ![Схема полусумматора](../.pic/Labs/lab_01_adder/fig_01.drawio.svg) diff --git a/Labs/01. Adder/README.md b/Labs/01. Adder/README.md index e9e1987..37cfe25 100644 --- a/Labs/01. Adder/README.md +++ b/Labs/01. Adder/README.md @@ -160,7 +160,7 @@ _Рисунок 3. Цифровая схема модуля half_adder, сген Схема похожа на _рис. 1_, но как проверить, что эта схема не содержит ошибок и делает именно то, что от нее ожидается? -Для этого необходимо провести моделирование этой схемы. Во время моделирования на вход схемы подаются входные воздействия. Каждое изменение входных сигналов схемы приводит к каскадному изменению состояния внутренних цепей, которые в итоге меняют выходные сигналы. +Для этого необходимо провести моделирование этой схемы. Во время моделирования на вход схемы подаются входные воздействия. Каждое изменение входных сигналов схемы приводит к каскадному изменению состояний внутренних цепей, которые в итоге меняют выходные сигналы. Подаваемые на схему входные воздействия формируются верификационным окружением. Верификационное окружение (или тестбенч) — это особый несинтезируемый модуль, который не имеет входных или выходных сигналов. Ему не нужны входные сигналы, поскольку он сам является генератором всех своих внутренних сигналов, и ему не нужны выходные сигналы, поскольку этот модуль ничего не вычисляет, только подает входные воздействия на проверяемый модуль. Внутри тестбенча можно использовать конструкции из несинтезируемого подмножества языка SystemVerilog, в частности программный блок `initial`, в котором команды выполняются последовательно, что делает этот блок чем-то отдаленно похожим на проверяющую программу. Поскольку изменение внутренних цепей происходит с некоторой задержкой относительно изменений входных сигналов, при моделировании есть возможность делать паузы между командами. Это делается с помощью специального символа #, за которым указывается количество отсчётов времени симуляции, которое нужно пропустить перед следующей командой. @@ -211,7 +211,7 @@ _Рисунок 4. Временная диаграмма, моделирующа _Рисунок 5. Схема четырехбитного сумматора._ -Фиолетовой линией на схеме показаны провода, соединяющие выходной бит переноса сумматора предыдущего разряда, с входным битом переноса сумматора следующего разряда. +Фиолетовой линией на схеме показаны провода, соединяющие выходной бит переноса сумматора предыдущего разряда с входным битом переноса сумматора следующего разряда. Как же реализовать модуль, состоящий из цепочки других модулей? Половину этой задачи мы уже сделали, когда писали тестбенч к однобитному полусумматору в _Листинге 2_ — мы создавали модуль внутри другого модуля и подключали к нему провода. Теперь надо сделать то же самое, только с чуть большим числом модулей. diff --git a/README.md b/README.md index 544c6ca..202f1c9 100644 --- a/README.md +++ b/README.md @@ -101,11 +101,11 @@
Радиотехники -Использование радиоволн сегодня помогает в решении огромного круга задач связанных с передачей информации/энергии на расстояние, локацией, позиционированием, изучением свойств объектов отражения и многим другим на что только фантазии хватит. На практике радиоволны оказываются удивительно полезными, и для того чтобы управлять ими и извлекать из них максимум, используются антенны. Эти устройства могут быть довольно сложными, и за ними должны стоять профессионалы, способные их создать. Управляют антеннами, контролируют их и получают с них информацию специальные устройства, которые, в конечном итоге, преобразуют радиосигналы в электрические цифровые, или наоборот. +Использование радиоволн сегодня помогает в решении огромного круга задач, связанных с передачей информации/энергии на расстояние, локацией, позиционированием, изучением свойств объектов отражения и многим другим на что только фантазии хватит. На практике радиоволны оказываются удивительно полезными, и для того, чтобы управлять ими и извлекать из них максимум, используются антенны. Эти устройства могут быть довольно сложными, и за ними должны стоять профессионалы, способные их создать. Управляют антеннами, контролируют их и получают с них информацию специальные устройства, которые, в конечном итоге, преобразуют радиосигналы в электрические цифровые, или наоборот. Современные микросхемы СВЧ (сверхвысоких частот), которые используются в антенных устройствах, часто являются программируемыми. Это означает, что они либо содержат в себе процессор, либо спроектированы для взаимодействия с процессорами. Чтобы раскрыть потенциал этих микросхем, вам нужно знать, как работают процессоры. Понимание их функций также пригодится в области радиотехники, особенно если вам нужно управлять сигналами в строгие временные рамки. -Радиотехника — это не только работа с радиосигналами, но и их обработка. Иногда нужно обрабатывать сигналы очень быстро. В таких случаях важно знать, какой вычислитель выбрать, чтобы обеспечить точность обработки в установленные временные рамки и при этом не превысить требования по энергопотреблению. Без понимания АПС вы не сможете решать такие задачи. Ведь приходится выбирать из множества устройств, включая микроконтроллеры и процессоры цифровой обработки сигналов с различными характеристиками, ПЛИС. А как это сделать, если даже не понимаешь что это такое. +Радиотехника — это не только работа с радиосигналами, но и их обработка. Иногда нужно обрабатывать сигналы очень быстро. В таких случаях важно знать, какой вычислитель выбрать, чтобы обеспечить точность обработки в установленные временные рамки и при этом не превысить требования по энергопотреблению. Без понимания АПС вы не сможете решать такие задачи. Ведь приходится выбирать из множества устройств, включая микроконтроллеры и процессоры цифровой обработки сигналов с различными характеристиками, ПЛИС. А как это сделать, если даже не понимаешь, что это такое. По сути, радиотехник – это специалист, который может не только посчитать антенну, но и создать ее, а также разработать систему управления, сбора и обработки данных с использованием знаний АПС. From 6acdb34a0a1961c2e045ccc2ef8a3f259f10220c Mon Sep 17 00:00:00 2001 From: BROsandr <53278658+BROsandr@users.noreply.github.com> Date: Tue, 19 Mar 2024 11:51:25 +0300 Subject: [PATCH 06/32] =?UTF-8?q?=D0=9B=D0=A04.=20=D0=A0=D0=B5=D1=84=D0=B0?= =?UTF-8?q?=D0=BA=D1=82=D0=BE=D1=80=20=D0=B4=D0=B5=D0=BC=D0=BE=D0=BD=D1=81?= =?UTF-8?q?=D1=82=D1=80=D0=B0=D1=86=D0=B8=D0=BE=D0=BD=D0=BD=D0=BE=D0=B3?= =?UTF-8?q?=D0=BE=20=D0=BC=D0=BE=D0=B4=D1=83=D0=BB=D1=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Демонстрационный модуль теперь только один --------- Co-authored-by: Andrei Solodovnikov --- .pic/Labs/board files/nexys_cobra.jpg | Bin 337800 -> 0 bytes .../nexys_cobra_operations.drawio.svg | 4 + .../nexys_cobra_structure.drawio.svg | 4 + .../board files/README.md | 66 ++- .../board files/demo.mem | 95 ---- .../board files/nexys_a7_100t.xdc | 110 ++-- .../board files/nexys_cybercobra.sv | 506 +++++++++++++++--- .../board files/nexys_cybercobra_demo.sv | 85 --- 8 files changed, 553 insertions(+), 317 deletions(-) delete mode 100644 .pic/Labs/board files/nexys_cobra.jpg create mode 100644 .pic/Labs/board files/nexys_cobra_operations.drawio.svg create mode 100644 .pic/Labs/board files/nexys_cobra_structure.drawio.svg delete mode 100644 Labs/04. Primitive programmable device/board files/demo.mem delete mode 100644 Labs/04. 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Main decoder/tb_decoder_riscv.sv | 1173 ++++++++++++++------- 1 file changed, 766 insertions(+), 407 deletions(-) diff --git a/Labs/05. Main decoder/tb_decoder_riscv.sv b/Labs/05. Main decoder/tb_decoder_riscv.sv index a8492bb..1fc5e62 100644 --- a/Labs/05. Main decoder/tb_decoder_riscv.sv +++ b/Labs/05. Main decoder/tb_decoder_riscv.sv @@ -2,460 +2,821 @@ * Project Name : Architectures of Processor Systems (APS) lab work * Organization : National Research University of Electronic Technology (MIET) * Department : Institute of Microdevices and Control Systems -* Author(s) : Nikita Bulavin -* Email(s) : nekkit6@edu.miet.ru +* Author(s) : Andrei Solodovnikov +* Email(s) : hepoh@org.miet.ru See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. * ------------------------------------------------------------------------------ */ + module tb_decoder_riscv(); import riscv_pkg::*; - parameter delay = 4; - parameter cycle = 200; // per one opcode + typedef class riscv_instr; + riscv_instr instr = new(); - reg [31:0] instr; - wire [1:0] a_sel; - wire [2:0] b_sel; - wire [ALU_OP_WIDTH-1:0] alu_op; - wire [2:0] csr_op; - wire csr_we; - wire mem_req; - wire mem_we; - wire [2:0] mem_size; - wire gpr_we; - wire [1:0] wb_sel; - wire illegal_instr; - wire branch; - wire jal; - wire jalr; - wire mret; + logic clk, test_has_been_finished; + logic [31:0] fetched_instr_i = '0; - reg a_sel_miss; - reg b_sel_miss; - reg alu_op_miss; - reg csr_op_miss; - reg csr_we_miss; - reg mem_req_miss; - reg mem_we_miss; - reg mem_size_miss; - reg gpr_we_miss; - reg wb_sel_miss; - reg illegal_miss; - reg branch_miss; - reg jal_miss; - reg jalr_miss; - reg mret_miss; + int err_count; - string opcode_type; - string instr_type; + //list of all valid opcodes + logic [4:0] opcode_array[11] = { + LOAD_OPCODE, + MISC_MEM_OPCODE, + OP_IMM_OPCODE, + AUIPC_OPCODE, + STORE_OPCODE, + OP_OPCODE, + LUI_OPCODE, + BRANCH_OPCODE, + JALR_OPCODE, + JAL_OPCODE, + SYSTEM_OPCODE + }; - decoder_riscv dut ( - .fetched_instr_i (instr), - .a_sel_o (a_sel), - .b_sel_o (b_sel), - .alu_op_o (alu_op), - .csr_op_o (csr_op), - .csr_we_o (csr_we), - .mem_req_o (mem_req), - .mem_we_o (mem_we), - .mem_size_o (mem_size), - .gpr_we_o (gpr_we), - .wb_sel_o (wb_sel), - .illegal_instr_o (illegal_instr), - .branch_o (branch), - .jal_o (jal), - .jalr_o (jalr), - .mret_o (mret) + /* + Since randomize with overconstraining slows down simulation, it has been + decided to make a list of all codes instead of looping over every possible + combination func3 and func7. + */ + logic [14:0] valid_codes[44] = { + {LOAD_OPCODE , 3'h0, 7'h00}, + {LOAD_OPCODE , 3'h1, 7'h00}, + {LOAD_OPCODE , 3'h2, 7'h00}, + {LOAD_OPCODE , 3'h4, 7'h00}, + {LOAD_OPCODE , 3'h5, 7'h00}, + {MISC_MEM_OPCODE, 3'h0, 7'h00}, + {OP_IMM_OPCODE , 3'h0, 7'h00}, + {OP_IMM_OPCODE , 3'h1, 7'h00}, + {OP_IMM_OPCODE , 3'h2, 7'h00}, + {OP_IMM_OPCODE , 3'h3, 7'h00}, + {OP_IMM_OPCODE , 3'h4, 7'h00}, + {OP_IMM_OPCODE , 3'h5, 7'h00}, + {OP_IMM_OPCODE , 3'h5, 7'h20}, + {OP_IMM_OPCODE , 3'h6, 7'h00}, + {OP_IMM_OPCODE , 3'h7, 7'h00}, + {AUIPC_OPCODE , 3'h0, 7'h00}, + {STORE_OPCODE , 3'h0, 7'h00}, + {STORE_OPCODE , 3'h1, 7'h00}, + {STORE_OPCODE , 3'h2, 7'h00}, + {OP_OPCODE , 3'h0, 7'h00}, + {OP_OPCODE , 3'h0, 7'h20}, + {OP_OPCODE , 3'h1, 7'h00}, + {OP_OPCODE , 3'h2, 7'h00}, + {OP_OPCODE , 3'h3, 7'h00}, + {OP_OPCODE , 3'h4, 7'h00}, + {OP_OPCODE , 3'h5, 7'h00}, + {OP_OPCODE , 3'h5, 7'h20}, + {OP_OPCODE , 3'h6, 7'h00}, + {OP_OPCODE , 3'h7, 7'h00}, + {LUI_OPCODE , 3'h0, 7'h00}, + {BRANCH_OPCODE , 3'h0, 7'h00}, + {BRANCH_OPCODE , 3'h1, 7'h00}, + {BRANCH_OPCODE , 3'h4, 7'h00}, + {BRANCH_OPCODE , 3'h5, 7'h00}, + {BRANCH_OPCODE , 3'h6, 7'h00}, + {BRANCH_OPCODE , 3'h7, 7'h00}, + {JALR_OPCODE , 3'h0, 7'h00}, + {JAL_OPCODE , 3'h0, 7'h00}, + {SYSTEM_OPCODE , 3'h1, 7'h00}, + {SYSTEM_OPCODE , 3'h2, 7'h00}, + {SYSTEM_OPCODE , 3'h3, 7'h00}, + {SYSTEM_OPCODE , 3'h5, 7'h00}, + {SYSTEM_OPCODE , 3'h6, 7'h00}, + {SYSTEM_OPCODE , 3'h7, 7'h00} + }; + + logic [14:0] invalid_codes[38] = { + {LOAD_OPCODE , 3'h3, 7'h00}, + {LOAD_OPCODE , 3'h6, 7'h00}, + {LOAD_OPCODE , 3'h7, 7'h00}, + {MISC_MEM_OPCODE, 3'h1, 7'h00}, + {MISC_MEM_OPCODE, 3'h2, 7'h00}, + {MISC_MEM_OPCODE, 3'h3, 7'h00}, + {MISC_MEM_OPCODE, 3'h4, 7'h00}, + {MISC_MEM_OPCODE, 3'h5, 7'h00}, + {MISC_MEM_OPCODE, 3'h6, 7'h00}, + {MISC_MEM_OPCODE, 3'h7, 7'h00}, + {OP_IMM_OPCODE , 3'h0, 7'h20}, + {OP_IMM_OPCODE , 3'h1, 7'h20}, + {OP_IMM_OPCODE , 3'h2, 7'h20}, + {OP_IMM_OPCODE , 3'h3, 7'h20}, + {OP_IMM_OPCODE , 3'h4, 7'h20}, + {OP_IMM_OPCODE , 3'h6, 7'h20}, + {OP_IMM_OPCODE , 3'h7, 7'h20}, + {STORE_OPCODE , 3'h3, 7'h00}, + {STORE_OPCODE , 3'h4, 7'h00}, + {STORE_OPCODE , 3'h5, 7'h00}, + {STORE_OPCODE , 3'h6, 7'h00}, + {STORE_OPCODE , 3'h7, 7'h00}, + {OP_OPCODE , 3'h1, 7'h20}, + {OP_OPCODE , 3'h2, 7'h20}, + {OP_OPCODE , 3'h3, 7'h20}, + {OP_OPCODE , 3'h4, 7'h20}, + {OP_OPCODE , 3'h6, 7'h20}, + {OP_OPCODE , 3'h7, 7'h20}, + {BRANCH_OPCODE , 3'h2, 7'h00}, + {BRANCH_OPCODE , 3'h3, 7'h00}, + {JALR_OPCODE , 3'h1, 7'h00}, + {JALR_OPCODE , 3'h2, 7'h00}, + {JALR_OPCODE , 3'h3, 7'h00}, + {JALR_OPCODE , 3'h4, 7'h00}, + {JALR_OPCODE , 3'h5, 7'h00}, + {JALR_OPCODE , 3'h6, 7'h00}, + {JALR_OPCODE , 3'h7, 7'h00}, + {SYSTEM_OPCODE , 3'h4, 7'h00} + }; + + initial begin + $display("Test has been started"); + $display( "\n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop(); + + valid_instrs_direct_test(); + valid_instrs_random_test(); + illegal_instr_direct_test(); + illegal_instrs_random_test(); + + $display("\nTest has been finished\nNumber of errors: %d\n", err_count); + test_has_been_finished = 1'b1; + $finish(); + end + + function void randomize_with_given_opcode(input logic[4:0] given_opcode); + if(!instr.randomize() with {(opcode == given_opcode);}) begin + $fatal(1, "Can't ranomize instr with opcode == %0h", given_opcode); + end + endfunction + + task valid_instrs_direct_test(); + /* + Enumeration of all possible instructions by every opcode, func3 and func7. + Additionally, ecall, ebreak and mret instructions are generated manually. + */ + foreach(valid_codes[i]) begin + if(instr.randomize() with {(opcode == valid_codes[i][14:10]) && (func3 == valid_codes[i][9:7]) && (func7 == valid_codes[i][6:0]);}) begin + @(posedge clk); + fetched_instr_i <= instr.bits; + end + else begin + $fatal(1, "Can't randomize instruction with opcode == %02h, func3 == %0h, func7 == %0h", valid_codes[i][14:10], valid_codes[i][9:7], valid_codes[i][6:0]); + end + end + for(int i = 0; i < 3; i++) begin + @(posedge clk); + fetched_instr_i <= instr.system_instrs[i]; + end + endtask + + task valid_instrs_random_test(); + /* + A thousand random instructions for each opcode. + */ + foreach(opcode_array[i]) begin + repeat(1e3) begin + randomize_with_given_opcode(opcode_array[i]); + @(posedge clk); + fetched_instr_i <= instr.bits; + end + end + endtask + + task illegal_instr_direct_test(); + /* + That's where real things are happening. + This task is intent to check all the ways to get illegal_instr_o goes 1. + Test trying: + - incorrect low 2 bits on every opcode; + - incorrect opcode; + - incorrect func3 and func7 where it's possible; + - incorrect fence, ecall, ebreak, mret instructions + */ + incorrect_low_two_bits_test(); + incorrect_opcode_test(); + incorrect_func3_func7_test(); + incorrect_hardcode_instrs(); + endtask + + task incorrect_low_two_bits_test(); + /* + For every opcode we generate a valid instruction and corrupt 2 low bits. + So for every opcode we try 3 different instructions. + */ + foreach(opcode_array[i]) begin + for(logic[1:0] j = 2'b00; j < 2'b11; j++) begin + randomize_with_given_opcode(opcode_array[i]); + @(posedge clk); + fetched_instr_i <= {instr.bits[31:2], j}; + end + end + endtask + + task incorrect_opcode_test(); + /* + For every instruction type (every opcode for the simplicity sake) we try + an instruction with incorrect opcode. + */ + foreach(opcode_array[i]) begin + automatic logic [4:0] incorrect_opcode; + for(logic[1:0] j = 2'b00; j < 2'b11; j++) begin + randomize_with_given_opcode(opcode_array[i]); + @(posedge clk); + assert(std::randomize(incorrect_opcode) with {!(incorrect_opcode inside { + LOAD_OPCODE, + MISC_MEM_OPCODE, + OP_IMM_OPCODE, + AUIPC_OPCODE, + STORE_OPCODE, + OP_OPCODE, + LUI_OPCODE, + BRANCH_OPCODE, + JALR_OPCODE, + JAL_OPCODE, + SYSTEM_OPCODE + });}); + fetched_instr_i <= {instr.bits[31:7], incorrect_opcode, 2'b11}; + end + end + endtask + + task incorrect_func3_func7_test(); + /* + This test is opposite of valid_instrs_direct_test: we are looping through + every illegal {opcode, func3, func7} combination and applying it onto + generated instruction. + */ + foreach(invalid_codes[i]) begin + randomize_with_given_opcode(invalid_codes[i][14:10]); + @(posedge clk); + fetched_instr_i <= {invalid_codes[i][6:0], instr.bits[24:15], invalid_codes[i][9:7], instr.bits[11:7], invalid_codes[i][14:10], 2'b11}; + end + endtask + + task incorrect_hardcode_instrs(); + /* + In this test we try to broke fence, ecall, ebreak and mret instructions: + - for the fence instr we need to make func3 to be not equal zero; + - for ecall, ebreak and mret instructions we need to corrupt imm, rs1, rd + values. + */ + + // Broken fence instructions + for(logic [3:0] i = 3'd1; i <= 4'd7; i++) begin + randomize_with_given_opcode(MISC_MEM_OPCODE); + @(posedge clk); + fetched_instr_i <= {instr.bits[31:15], i, instr.bits[11:0]}; + end + + // Broken ecall, ebreak, mret instructions + for(logic [2:0] j = 3'd0; j <= 3'd3; j++) begin + @(posedge clk); + // broken imm field + fetched_instr_i <= {12'd2, instr.system_instrs[j][19:0]}; + @(posedge clk); + // broken rs1 field + fetched_instr_i <= {instr.system_instrs[j][31:20], 5'd1, instr.system_instrs[j][14:0]}; + @(posedge clk); + // broken rd field + fetched_instr_i <= {instr.system_instrs[j][31:12], 5'd1, instr.system_instrs[j][6:0]}; + end + endtask + + task illegal_instrs_random_test(); + /* + It's inefficiently to randomize all 32 bits of instructions since most + of them would be illegal by opcode or low 2 bits. + This test will construct instructions from valid parts but in random order + which will cause illegal instructions to be produced. + Additionally test will insert illegal parts with low chance. + */ + automatic logic [2:0] func3; + automatic logic [6:0] func7; + automatic logic [4:0] opcode; + automatic logic [4:0] rs1, rs2, rd; + automatic logic [1:0] low_bits; + automatic logic [9:0] mutation; + repeat(1e4) begin + assert(std::randomize(mutation)); + // we want to broke (invert constraint of) func3 if + // 9's bit is 1 while six lower bits are 0 + if(mutation[9] & !(|mutation[5:0])) begin + assert(std::randomize(func7 ) with {!(func7 inside {7'h0, 7'h20});}); + end + else begin + assert(std::randomize(func7 ) with { (func7 inside {7'h0, 7'h20});}); + end + if(mutation[8] & !(|mutation[5:0])) begin + assert(std::randomize(opcode ) with {!(opcode inside { + LOAD_OPCODE, + MISC_MEM_OPCODE, + OP_IMM_OPCODE, + AUIPC_OPCODE, + STORE_OPCODE, + OP_OPCODE, + LUI_OPCODE, + BRANCH_OPCODE, + JALR_OPCODE, + JAL_OPCODE, + SYSTEM_OPCODE + });}); + end + else begin + assert(std::randomize(opcode ) with { (opcode inside { + LOAD_OPCODE, + MISC_MEM_OPCODE, + OP_IMM_OPCODE, + AUIPC_OPCODE, + STORE_OPCODE, + OP_OPCODE, + LUI_OPCODE, + BRANCH_OPCODE, + JALR_OPCODE, + JAL_OPCODE, + SYSTEM_OPCODE + });}); + end + if(mutation[7] & !(|mutation[5:0])) begin + assert(std::randomize(low_bits ) with {!(low_bits == 2'b11);}); + end + else begin + assert(std::randomize(low_bits ) with { (low_bits == 2'b11);}); + end + assert(std::randomize(func3)); assert(std::randomize(rs1)); assert(std::randomize(rs2)); assert(std::randomize(rd)); + @(posedge clk); + fetched_instr_i <= {func7, rs2, rs1, func3, rd, opcode, low_bits}; + end + endtask + + bit test_paused_by_errs; + initial begin + clk = '0; + test_has_been_finished = '0; + err_count = '0; + test_paused_by_errs = '0; + end + + always #5 clk = ~clk; + always @(posedge clk) begin + if(test_has_been_finished) begin + $finish(); + end + end + + always @(posedge clk) begin + if((err_count >= 10) & !test_paused_by_errs) begin + test_paused_by_errs = '1; + $display("\nTest has been stopped after 10 errors"); + $stop(); + end + end + + logic [1:0] a_sel_o; + logic [2:0] b_sel_o; + logic [4:0] alu_op_o; + logic [2:0] csr_op_o; + logic csr_we_o; + logic mem_req_o; + logic mem_we_o; + logic [2:0] mem_size_o; + logic gpr_we_o; + logic [1:0] wb_sel_o; + logic illegal_instr_o; + logic branch_o; + logic jal_o; + logic jalr_o; + logic mret_o; + + logic [1:0] grm_a_sel_o; + logic [2:0] grm_b_sel_o; + logic [4:0] grm_alu_op_o; + logic [2:0] grm_csr_op_o; + logic grm_csr_we_o; + logic grm_mem_req_o; + logic grm_mem_we_o; + logic [2:0] grm_mem_size_o; + logic grm_gpr_we_o; + logic [1:0] grm_wb_sel_o; + logic grm_illegal_instr_o; + logic grm_branch_o; + logic grm_jal_o; + logic grm_jalr_o; + logic grm_mret_o; + + + decoder_riscv DUT(.*); + + decoder_riscv_ref GRM( + .fetched_instr_i (fetched_instr_i ), + .a_sel_o (grm_a_sel_o ), + .b_sel_o (grm_b_sel_o ), + .alu_op_o (grm_alu_op_o ), + .csr_op_o (grm_csr_op_o ), + .csr_we_o (grm_csr_we_o ), + .mem_req_o (grm_mem_req_o ), + .mem_we_o (grm_mem_we_o ), + .mem_size_o (grm_mem_size_o ), + .gpr_we_o (grm_gpr_we_o ), + .wb_sel_o (grm_wb_sel_o ), + .illegal_instr_o (grm_illegal_instr_o), + .branch_o (grm_branch_o ), + .jal_o (grm_jal_o ), + .jalr_o (grm_jalr_o ), + .mret_o (grm_mret_o ) ); - - decoder_riscv_ref grm(.fetched_instr_i (instr)); - wire [4:0] opcode; - assign opcode = instr[6:2]; + logic [4:0] opcode; + logic [2:0] func3; - always @(*) begin + logic a_sel_check ; + logic b_sel_check ; + logic alu_op_check ; + logic csr_op_check ; + logic csr_we_check ; + logic mem_req_check ; + logic mem_we_check ; + logic mem_size_check; + logic gpr_we_check ; + logic wb_sel_check ; + logic branch_check ; + logic jal_check ; + logic jalr_check ; + logic mret_check ; + + assign opcode = fetched_instr_i[6:2]; + assign func3 = fetched_instr_i[14:12]; + + assign a_sel_check = !(opcode inside {MISC_MEM_OPCODE, SYSTEM_OPCODE}); + assign b_sel_check = !(opcode inside {MISC_MEM_OPCODE, SYSTEM_OPCODE}); + assign alu_op_check = !(opcode inside {MISC_MEM_OPCODE, SYSTEM_OPCODE}); + assign csr_op_check = (opcode == SYSTEM_OPCODE) && (func3 != 3'd0); + assign csr_we_check = 1'b1; + assign mem_req_check = 1'b1; + assign mem_we_check = 1'b1; + assign mem_size_check = (opcode inside {LOAD_OPCODE, STORE_OPCODE}); + assign gpr_we_check = 1'b1; + assign wb_sel_check = !(opcode inside {MISC_MEM_OPCODE, BRANCH_OPCODE}) && (!(opcode == SYSTEM_OPCODE) | ((opcode == SYSTEM_OPCODE) & (func3 != 3'd0))); // (opcode == SYSTEM_OPCODE) -> (func3 != 3'd0) + assign branch_check = 1'b1; + assign jal_check = 1'b1; + assign jalr_check = 1'b1; + assign mret_check = 1'b1; + + string instr_str; + string raw_instr; + + illegal_instr_prop: assert property( + @(posedge clk) + (grm_illegal_instr_o === illegal_instr_o) + ) + else begin + $display("illegal_instr_o value is incorrect ( %b instead of %b), instruction: %s %s", illegal_instr_o, grm_illegal_instr_o , raw_instr, instr_str ); + err_count++; + end + + a_sel_prop : assert property ( + @(posedge clk) disable iff(grm_illegal_instr_o) + a_sel_check |-> (grm_a_sel_o === a_sel_o ) + ) + else begin + $display("a_sel_o value is incorrect ( %02b instead of %02b), instruction: %s %s", a_sel_o , grm_a_sel_o , raw_instr, instr_str ); + err_count++; + end + + b_sel_prop : assert property ( + @(posedge clk) disable iff(grm_illegal_instr_o) + b_sel_check |-> (grm_b_sel_o === b_sel_o ) + ) + else begin + $display("b_sel_o value is incorrect ( %03b instead of %03b), instruction: %s %s", b_sel_o , grm_b_sel_o , raw_instr, instr_str ); + err_count++; + end + + alu_op_prop : assert property ( + @(posedge clk) disable iff(grm_illegal_instr_o) + alu_op_check |-> (grm_alu_op_o === alu_op_o ) + ) + else begin + $display("alu_op_o value is incorrect (%05b instead of %05b), instruction: %s %s", alu_op_o , grm_alu_op_o, raw_instr, instr_str ); + err_count++; + end + + csr_op_prop : assert property ( + @(posedge clk) disable iff(grm_illegal_instr_o) + csr_op_check |-> (grm_csr_op_o === csr_op_o ) + ) + else begin + $display("csr_op_o value is incorrect ( %03b instead of %03b), instruction: %s %s", csr_op_o , grm_csr_op_o, raw_instr, instr_str ); + err_count++; + end + + csr_we_prop : assert property ( + @(posedge clk) + csr_we_check |-> (grm_csr_we_o === csr_we_o ) + ) + else begin + $display("csr_we_o value is incorrect ( %b instead of %b), instruction: %s %s", csr_we_o , grm_csr_we_o, raw_instr, instr_str ); + err_count++; + end + + mem_req_prop : assert property ( + @(posedge clk) + mem_req_check |-> (grm_mem_req_o === mem_req_o ) + ) + else begin + $display("mem_req_o value is incorrect ( %b instead of %b), instruction: %s %s", mem_req_o , grm_mem_req_o, raw_instr, instr_str ); + err_count++; + end + + mem_we_prop : assert property ( + @(posedge clk) + mem_we_check |-> (grm_mem_we_o === mem_we_o ) + ) + else begin + $display("mem_we_o value is incorrect ( %b instead of %b), instruction: %s %s", mem_we_o , grm_mem_we_o, raw_instr, instr_str ); + err_count++; + end + + mem_size_prop: assert property ( + @(posedge clk) disable iff(grm_illegal_instr_o) + mem_size_check |-> (grm_mem_size_o === mem_size_o) + ) + else begin + $display("mem_size_o value is incorrect ( %03b instead of %03b), instruction: %s %s", mem_size_o, grm_mem_size_o, raw_instr, instr_str); + err_count++; + end + + gpr_we_prop : assert property ( + @(posedge clk) + gpr_we_check |-> (grm_gpr_we_o === gpr_we_o ) + ) + else begin + $display("gpr_we_o value is incorrect ( %b instead of %b), instruction: %s %s", gpr_we_o , grm_gpr_we_o, raw_instr, instr_str ); + err_count++; + end + + wb_sel_prop : assert property ( + @(posedge clk) disable iff(grm_illegal_instr_o) + wb_sel_check |-> (grm_wb_sel_o === wb_sel_o ) + ) + else begin + $display("wb_sel_o value is incorrect ( %b instead of %b), instruction: %s %s", wb_sel_o , grm_wb_sel_o, raw_instr, instr_str ); + err_count++; + end + + branch_prop : assert property ( + @(posedge clk) + branch_check |-> (grm_branch_o === branch_o ) + ) + else begin + $display("branch_o value is incorrect ( %b instead of %b), instruction: %s %s", branch_o , grm_branch_o, raw_instr, instr_str ); + err_count++; + end + + jal_prop : assert property ( + @(posedge clk) + jal_check |-> (grm_jal_o === jal_o ) + ) + else begin + $display("jal_o value is incorrect ( %b instead of %b), instruction: %s %s", jal_o , grm_jal_o , raw_instr, instr_str ); + err_count++; + end + + jalr_prop : assert property ( + @(posedge clk) + jalr_check |-> (grm_jalr_o === jalr_o ) + ) + else begin + $display("jalr_o value is incorrect ( %b instead of %b), instruction: %s %s", jalr_o , grm_jalr_o , raw_instr, instr_str ); + err_count++; + end + + mret_prop : assert property ( + @(posedge clk) + mret_check |-> (grm_mret_o === mret_o ) + ) + else begin + $display("mret_o value is incorrect ( %b instead of %b), instruction: %s %s", mret_o , grm_mret_o , raw_instr, instr_str ); + err_count++; + end + + always_comb begin case (opcode) LUI_OPCODE, AUIPC_OPCODE, JAL_OPCODE: - instr_type = $sformatf("%020b %05b %07b ", instr[31:12], instr[11:7], instr[6:0]); + raw_instr = $sformatf("%020b %05b %07b " , fetched_instr_i[31:12], fetched_instr_i[11:7], fetched_instr_i[6:0]); JALR_OPCODE, LOAD_OPCODE, OP_IMM_OPCODE, SYSTEM_OPCODE: - instr_type = $sformatf("%012b %05b %03b %05b %07b ", instr[31:20], instr[19:15], instr[14:12], instr[11:7], instr[6:0]); + raw_instr = $sformatf("%012b %05b %03b %05b %07b " , fetched_instr_i[31:20], fetched_instr_i[19:15], fetched_instr_i[14:12], fetched_instr_i[11:7], fetched_instr_i[6:0]); BRANCH_OPCODE, STORE_OPCODE, OP_OPCODE: - instr_type = $sformatf("%07b %05b %05b %03b %05b %07b", instr[31:25], instr[24:20], instr[19:15], instr[14:12], instr[11:7], instr[6:0]); - MISC_MEM_OPCODE: - instr_type = $sformatf("%017b %03b %05b %07b ", instr[31:15], instr[14:12], instr[11:7], instr[6:0]); - default: - instr_type = $sformatf("%032b ", instr); + raw_instr = $sformatf("%07b %05b %05b %03b %05b %07b", fetched_instr_i[31:25], fetched_instr_i[24:20], fetched_instr_i[19:15], fetched_instr_i[14:12], fetched_instr_i[11:7], fetched_instr_i[6:0]); + MISC_MEM_OPCODE: + raw_instr = $sformatf("%017b %03b %05b %07b " , fetched_instr_i[31:15], fetched_instr_i[14:12], fetched_instr_i[11:7], fetched_instr_i[6:0]); + default: + raw_instr = $sformatf("%032b " , fetched_instr_i); endcase end - always @(*) begin - a_sel_miss = 'b0; - b_sel_miss = 'b0; - alu_op_miss = 'b0; - csr_op_miss = 'b0; - csr_we_miss = 'b0; - mem_req_miss = 'b0; - mem_we_miss = 'b0; - mem_size_miss = 'b0; - gpr_we_miss = 'b0; - wb_sel_miss = 'b0; - illegal_miss = 'b0; - branch_miss = 'b0; - jal_miss = 'b0; - jalr_miss = 'b0; - mret_miss = 'b0; - illegal_miss = grm.illegal_instr_o !== illegal_instr; - case (opcode) - LOAD_OPCODE, STORE_OPCODE: - begin - a_sel_miss = (grm.a_sel_o !== a_sel) & !illegal_instr; - b_sel_miss = (grm.b_sel_o !== b_sel) & !illegal_instr; - alu_op_miss = (grm.alu_op_o !== alu_op) & !illegal_instr; - csr_we_miss = (grm.csr_we_o !== csr_we); - mem_req_miss = grm.mem_req_o !== mem_req; - mem_we_miss = grm.mem_we_o !== mem_we; - mem_size_miss = (grm.mem_size_o !== mem_size) & !illegal_instr; - gpr_we_miss = grm.gpr_we_o !== gpr_we; - wb_sel_miss = (grm.wb_sel_o !== wb_sel) & !illegal_instr; - branch_miss = grm.branch_o !== branch; - jal_miss = grm.jal_o !== jal; - jalr_miss = grm.jalr_o !== jalr; - mret_miss = grm.mret_o !== mret; - end - - JAL_OPCODE, JALR_OPCODE, - AUIPC_OPCODE, - OP_IMM_OPCODE, OP_OPCODE: - begin - a_sel_miss = (grm.a_sel_o !== a_sel) & !illegal_instr; - b_sel_miss = (grm.b_sel_o !== b_sel) & !illegal_instr; - alu_op_miss = (grm.alu_op_o !== alu_op) & !illegal_instr; - csr_we_miss = (grm.csr_we_o !== csr_we); - mem_req_miss = grm.mem_req_o !== mem_req; - mem_we_miss = grm.mem_we_o !== mem_we; - //mem_size_miss = (grm.mem_size_o !== mem_size) & !illegal_instr; - gpr_we_miss = grm.gpr_we_o !== gpr_we; - wb_sel_miss = (grm.wb_sel_o !== wb_sel) & !illegal_instr; - branch_miss = grm.branch_o !== branch; - jal_miss = grm.jal_o !== jal; - jalr_miss = grm.jalr_o !== jalr; - mret_miss = grm.mret_o !== mret; - end - - BRANCH_OPCODE: - begin - a_sel_miss = (grm.a_sel_o !== a_sel) & !illegal_instr; - b_sel_miss = (grm.b_sel_o !== b_sel) & !illegal_instr; - alu_op_miss = (grm.alu_op_o !== alu_op) & !illegal_instr; - csr_we_miss = (grm.csr_we_o !== csr_we); - mem_req_miss = grm.mem_req_o !== mem_req; - mem_we_miss = grm.mem_we_o !== mem_we; - //mem_size_miss = (grm.mem_size_o !== mem_size) & !illegal_instr; - gpr_we_miss = grm.gpr_we_o !== gpr_we; - //wb_sel_miss = (grm.wb_sel_o !== wb_sel) & !illegal_instr; - branch_miss = grm.branch_o !== branch; - jal_miss = grm.jal_o !== jal; - jalr_miss = grm.jalr_o !== jalr; - mret_miss = grm.mret_o !== mret; - end - - LUI_OPCODE: begin - a_sel_miss = (grm.a_sel_o !== a_sel) & !illegal_instr; - b_sel_miss = (grm.b_sel_o !== b_sel) & !illegal_instr; - alu_op_miss = ((alu_op !== ALU_ADD)&(alu_op !== ALU_XOR)&(alu_op !== ALU_OR)) & !illegal_instr; - csr_we_miss = (grm.csr_we_o !== csr_we); - mem_req_miss = grm.mem_req_o !== mem_req; - mem_we_miss = grm.mem_we_o !== mem_we; - //mem_size_miss = (grm.mem_size_o !== mem_size) & !illegal_instr; - gpr_we_miss = grm.gpr_we_o !== gpr_we; - wb_sel_miss = (grm.wb_sel_o !== wb_sel) & !illegal_instr; - branch_miss = grm.branch_o !== branch; - jal_miss = grm.jal_o !== jal; - jalr_miss = grm.jalr_o !== jalr; - mret_miss = grm.mret_o !== mret; - end - - SYSTEM_OPCODE: begin - //a_sel_miss = (grm.a_sel_o !== a_sel) & !illegal_instr; - //b_sel_miss = (grm.b_sel_o !== b_sel) & !illegal_instr; - //alu_op_miss = ((alu_op !== ALU_ADD)&(alu_op !== ALU_XOR)&(alu_op !== ALU_OR)) & !illegal_instr; - csr_we_miss = (grm.csr_we_o !== csr_we); - mem_req_miss = grm.mem_req_o !== mem_req; - mem_we_miss = grm.mem_we_o !== mem_we; - //mem_size_miss = (grm.mem_size_o !== mem_size) & !illegal_instr; - gpr_we_miss = grm.gpr_we_o !== gpr_we; - wb_sel_miss = (grm.wb_sel_o !== wb_sel) & !illegal_instr & !mret; - branch_miss = grm.branch_o !== branch; - jal_miss = grm.jal_o !== jal; - jalr_miss = grm.jalr_o !== jalr; - mret_miss = grm.mret_o !== mret; - end - default: //MISC_MEM_OPCODE and other - begin - //a_sel_miss = grm.a_sel_o !== a_sel; - //b_sel_miss = grm.b_sel_o !== b_sel; - //alu_op_miss = grm.alu_op_o !== alu_op; - csr_we_miss = (grm.csr_we_o !== csr_we); - mem_req_miss = grm.mem_req_o !== mem_req; - mem_we_miss = grm.mem_we_o !== mem_we; - //mem_size_miss = grm.mem_size_o !== mem_size; - gpr_we_miss = grm.gpr_we_o !== gpr_we; - //wb_sel_miss = grm.wb_sel_o !== wb_sel; - branch_miss = grm.branch_o !== branch; - jal_miss = grm.jal_o !== jal; - jalr_miss = grm.jalr_o !== jalr; - mret_miss = grm.mret_o !== mret; - end - endcase - end - - integer X; - reg [$clog2(cycle+1)-1:0] V; - integer error; - - initial begin - $timeformat(-9, 2, " ns", 3); - error = 0; - end - - initial begin - $display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop(); - - for (V=0; V !(func3 inside {3'h3, 3'h6, 3'h7});} + + constraint misc_mem_opcode { (opcode == MISC_MEM_OPCODE) -> (func3 == 3'b000);} + + constraint op_imm_opcode1 {((opcode == OP_IMM_OPCODE ) && (func3 == 3'h1)) -> (func7 == 7'h00);} + constraint op_imm_opcode2 {((opcode == OP_IMM_OPCODE ) && (func3 == 3'h5)) -> (func7 inside {7'h00, 7'h20});} + + constraint store_opcode { (opcode == STORE_OPCODE ) -> (func3 inside {3'h0, 3'h1, 3'h2});} + + constraint op_opcode1 {((opcode == OP_OPCODE ) && (func3 inside {3'b000, 3'b101})) -> (func7 inside {7'h00, 7'h20});} + constraint op_opcode2 {((opcode == OP_OPCODE ) && !(func3 inside {3'b000, 3'b101})) -> (func7 == 7'h00);} + + constraint branch_opcode { (opcode == BRANCH_OPCODE ) -> !(func3 inside {3'h2, 3'h3});} + + constraint jalr_opcode { (opcode == JALR_OPCODE ) -> (func3 == 3'h0);} + + constraint system_opcode { (opcode == SYSTEM_OPCODE ) -> !(func3 == 3'h4);} + + function void post_randomize(); + case(opcode) + LOAD_OPCODE, MISC_MEM_OPCODE, JALR_OPCODE: begin + bits = {imm[11:0], rs1, func3, rd, opcode, 2'b11}; + end + OP_IMM_OPCODE: begin + if(func3 inside {3'h1, 3'h5}) begin + bits = {func7, shamt, rs1, func3, rd, opcode, 2'b11}; + end + else begin + bits = {imm[11:0], rs1, func3, rd, opcode, 2'b11}; + end + end + AUIPC_OPCODE, LUI_OPCODE: begin + bits = {imm, opcode, 2'b11}; + end + STORE_OPCODE: begin + bits = {imm[11:5], rs2, rs1, func3, imm[4:0], opcode, 2'b11}; + end + OP_OPCODE: begin + bits = {func7, rs2, rs1, func3, rd, opcode, 2'b11}; + end + BRANCH_OPCODE: begin + bits = {imm[12], imm[10:5], rs2, rs1, func3, imm[4:1], imm[11], opcode, 2'b11}; + end + JAL_OPCODE: begin + bits = {imm[20], imm[10:1], imm[11], imm[19:12], rd, opcode, 2'b11}; + end + SYSTEM_OPCODE: begin + if(func3 == 3'h0) begin + bits = system_instrs[$urandom_range(3)]; + end + else begin + bits = {imm[11:0], rs1, func3, rd, opcode, 2'b11}; + end + end + default: begin + $fatal(1, "Missing opcode %0h in post_randomize", opcode); + end + endcase + endfunction + + endclass + endmodule -////////////////////////////////////////////////////////////////////////////////// -// Company: MIET -// Engineer: Alexey Kozin -// -// Create Date: 10/08/2023 07:39:15 AM -// Design Name: -// Module Name: decoder_riscv -// Project Name: RISCV_practicum -// Target Devices: Nexys A7-100T -// Tool Versions: -// Description: main decoder for risc-v processor -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -////////////////////////////////////////////////////////////////////////////////// +/* ----------------------------------------------------------------------------- +* Project Name : Architectures of Processor Systems (APS) lab work +* Organization : National Research University of Electronic Technology (MIET) +* Department : Institute of Microdevices and Control Systems +* Author(s) : Alexey Kozin +* Email(s) : @edu.miet.ru +See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. +* ------------------------------------------------------------------------------ +*/ module gpr_we_table (gis_ew_rpg, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2); output logic gis_ew_rpg; input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2; @@ -536,8 +897,6 @@ module csr_we_table (gis_ew_rsc, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_ endcase endmodule - - module mem_req_table (gis_qer_mem, edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2); output logic gis_qer_mem; input edocpo_6, edocpo_5, edocpo_4, edocpo_3, edocpo_2; From becb469dcb244ba268cc9d8c6c8ba6c5438eac75 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Mon, 1 Apr 2024 11:31:25 +0200 Subject: [PATCH 20/32] =?UTF-8?q?=D0=9B=D0=A03.=20=D0=9E=D0=BF=D0=B8=D1=81?= =?UTF-8?q?=D0=B0=D0=BD=D0=B8=D0=B5=20=D0=B7=D0=B0=D0=BF=D1=80=D0=BE=D1=81?= =?UTF-8?q?=D0=B0=20=D0=BD=D0=B0=20=D1=87=D1=82=D0=B5=D0=BD=D0=B8=D0=B5=20?= =?UTF-8?q?=D0=B2=20=D1=8F=D0=B2=D0=BD=D0=BE=D0=BC=20=D0=B2=D0=B8=D0=B4?= =?UTF-8?q?=D0=B5?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit В методичке был люфт по поводу способов реализации запроса на чтение: - только по сигналу mem_req_i (в этом случае запрос на чтение производился при любом значении сигнала mem_we_i); - при одновременном выполнении mem_req_i == 1 и mem_we_i == 0. --- Labs/03. Register file and memory/README.md | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Labs/03. Register file and memory/README.md b/Labs/03. Register file and memory/README.md index fa9886b..f46e522 100644 --- a/Labs/03. Register file and memory/README.md +++ b/Labs/03. Register file and memory/README.md @@ -267,6 +267,9 @@ mоdulе data_mеm( Если `mem_req_i == 1` и `write_enable_i == 1`, то происходит запрос на запись в память. В этом случае, необходимо записать значение `write_data_i` в ячейку по адресу `addr_i[13:2]`. Во всех других случаях (любой из сигналов `mem_req_i`, `write_enable_i` равен нулю), запись в память не производится. +Если `mem_req_i == 1` и `write_enable_i == 0`, то происходит запрос на чтение из памяти. В этом случае, необходимо записать в выходной регистр `read_data_o` значение из ячейки по адресу `addr_i[13:2]`. Во всех других случаях чтение из памяти не производится (`read_data_o` сохраняет предыдущее значение). + + ### 3. Регистровый файл У данного модуля будет восемь входных/выходных сигналов: From 161369f7fcad876b93798b0a1a4b580a1fe1d116 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Mon, 1 Apr 2024 16:14:33 +0300 Subject: [PATCH 21/32] =?UTF-8?q?=D0=9B=D0=A05.=20=D0=94=D0=BE=D1=80=D0=B0?= =?UTF-8?q?=D0=B1=D0=BE=D1=82=D0=BA=D0=B0=20=D1=82=D0=B1?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Правка выравниваний при выводе, причесывание циклов. --- Labs/05. Main decoder/tb_decoder_riscv.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Labs/05. Main decoder/tb_decoder_riscv.sv b/Labs/05. Main decoder/tb_decoder_riscv.sv index 1fc5e62..83d32c4 100644 --- a/Labs/05. Main decoder/tb_decoder_riscv.sv +++ b/Labs/05. Main decoder/tb_decoder_riscv.sv @@ -203,7 +203,7 @@ module tb_decoder_riscv(); So for every opcode we try 3 different instructions. */ foreach(opcode_array[i]) begin - for(logic[1:0] j = 2'b00; j < 2'b11; j++) begin + for(int j = 0; j < 3; j++) begin randomize_with_given_opcode(opcode_array[i]); @(posedge clk); fetched_instr_i <= {instr.bits[31:2], j}; @@ -218,7 +218,7 @@ module tb_decoder_riscv(); */ foreach(opcode_array[i]) begin automatic logic [4:0] incorrect_opcode; - for(logic[1:0] j = 2'b00; j < 2'b11; j++) begin + for(int j = 0; j < 3; j++) begin randomize_with_given_opcode(opcode_array[i]); @(posedge clk); assert(std::randomize(incorrect_opcode) with {!(incorrect_opcode inside { @@ -261,14 +261,14 @@ module tb_decoder_riscv(); */ // Broken fence instructions - for(logic [3:0] i = 3'd1; i <= 4'd7; i++) begin + for(int i = 1; i < 8; i++) begin randomize_with_given_opcode(MISC_MEM_OPCODE); @(posedge clk); fetched_instr_i <= {instr.bits[31:15], i, instr.bits[11:0]}; end // Broken ecall, ebreak, mret instructions - for(logic [2:0] j = 3'd0; j <= 3'd3; j++) begin + for(int j = 0; j < 3; j++) begin @(posedge clk); // broken imm field fetched_instr_i <= {12'd2, instr.system_instrs[j][19:0]}; @@ -558,7 +558,7 @@ module tb_decoder_riscv(); wb_sel_check |-> (grm_wb_sel_o === wb_sel_o ) ) else begin - $display("wb_sel_o value is incorrect ( %b instead of %b), instruction: %s %s", wb_sel_o , grm_wb_sel_o, raw_instr, instr_str ); + $display("wb_sel_o value is incorrect ( %b instead of %b), instruction: %s %s", wb_sel_o , grm_wb_sel_o, raw_instr, instr_str ); err_count++; end From eacb7276304de876f0b4876a71dccf141fa0bacb Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 2 Apr 2024 07:37:02 +0300 Subject: [PATCH 22/32] =?UTF-8?q?=D0=9B=D0=A04.=20=D0=9F=D0=B5=D1=80=D0=B5?= =?UTF-8?q?=D0=B8=D0=BC=D0=B5=D0=BD=D0=BE=D0=B2=D0=B0=D0=BD=D0=B8=D0=B5=20?= =?UTF-8?q?example.mem=20->=20program.mem?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit При рефакторе киберкобры, было решено унифицировать примеры программ, однако забыли переименовать оставленный файл под вариант, инициализирующий память инструкций в третьей лабе. --- .../{example.mem => program.mem} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename Labs/04. Primitive programmable device/{example.mem => program.mem} (100%) diff --git a/Labs/04. Primitive programmable device/example.mem b/Labs/04. Primitive programmable device/program.mem similarity index 100% rename from Labs/04. Primitive programmable device/example.mem rename to Labs/04. Primitive programmable device/program.mem From 6d0af977c777677b417f8fa40a08159b106753cf Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 2 Apr 2024 07:40:26 +0300 Subject: [PATCH 23/32] =?UTF-8?q?=D0=9B=D0=A05.=20=D0=A1=D1=82=D0=B8=D0=BB?= =?UTF-8?q?=D0=B8=D1=81=D1=82=D0=B8=D1=87=D0=B5=D1=81=D0=BA=D0=B8=D0=B5=20?= =?UTF-8?q?=D0=BF=D1=80=D0=B0=D0=B2=D0=BA=D0=B8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/05. Main decoder/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Labs/05. Main decoder/README.md b/Labs/05. Main decoder/README.md index 174c170..d9ec20e 100644 --- a/Labs/05. Main decoder/README.md +++ b/Labs/05. Main decoder/README.md @@ -79,7 +79,7 @@ _Таблица 3. Инструкции набора RV32I с приведени Обратите внимание на операции `slli`, `srli` и `srai` (операции сдвига на константную величину). У этих инструкций немного измененный формат кодирования **I\***. Формат кодирования **I** предоставляет 12-битную константу. Сдвиг 32-битного числа более, чем на 31 не имеет смысла. Для кодирования числа 31 требуется всего 5 бит. Выходит, что из 12 бит константы используется только 5 бит для операции сдвига, а оставшиеся 7 бит – не используются. А, главное (какое совпадение!), эти 7 бит находятся ровно в том же месте, где у других инструкций находится поле `func7`. Поэтому, чтобы у инструкций `slli`, `srli` и `srai` использующих формат **I** не пропадала эта часть поля, к ней относятся как к полю `func7`. -Также обратите внимание на инструкции `ecall`, `ebreak` и `mret`. Все эти инструкции I-типа имеют поле func3 равное нулю. С точки зрения декодирования инструкции I-типа, это одна и та же инструкция с разными полями. Однако конкретно в этом случае (SYSTEM_OPCODE и `func3 == 0`) эти инструкции должны рассматриваться как совокупность всех 32-бит сразу (см. _Таблицу 1_). +Также обратите внимание на инструкции `ecall`, `ebreak` и `mret`. Все эти инструкции I-типа имеют поле func3, равное нулю. С точки зрения декодирования инструкции I-типа, это одна и та же инструкция с разными полями. Однако конкретно в данном случае (SYSTEM_OPCODE и `func3 == 0`) эти инструкции должны рассматриваться как совокупность всех 32-бит сразу (см. _Таблицу 1_). ### Предлагаемая микроархитектура процессора RISC-V From b10f831825e70608b2818bd68b5764653d0218f8 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 2 Apr 2024 11:59:12 +0300 Subject: [PATCH 24/32] =?UTF-8?q?=D0=9B=D0=A06.=20=D0=98=D1=81=D0=BF=D1=80?= =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BB=D0=B8=D1=81?= =?UTF-8?q?=D1=82=D0=B8=D0=BD=D0=B3=D0=B0=20=D1=81=20=D0=B4=D0=B2=D0=BE?= =?UTF-8?q?=D0=B8=D1=87=D0=BD=D1=8B=D0=BC=20=D0=BA=D0=BE=D0=B4=D0=BE=D0=BC?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Листинг не соответствовал коду на ассемблере и содержимому файла program.mem --- Labs/06. Datapath/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Labs/06. Datapath/README.md b/Labs/06. Datapath/README.md index a8bc6d4..c250beb 100644 --- a/Labs/06. Datapath/README.md +++ b/Labs/06. Datapath/README.md @@ -150,8 +150,8 @@ _Рисунок 2. Микроархитектура процессора._ 20: 0000000 11111 00101 001 00111 0010011 24: 0100000 00001 00111 101 01000 0010011 28: 0000000 11101 01000 101 01001 0010011 -2C: 11011110101011011100 01010 0110111 -30: 111010101111 01010 000 01010 0010011 +2C: 11111010110111101100 01010 0110111 +30: 101010111110 01010 000 01010 0010011 34: 0000000 01010 00100 010 00000 0100011 38: 0000000 01010 00100 001 00110 0100011 3C: 0000000 01010 00100 000 01011 0100011 @@ -159,7 +159,7 @@ _Рисунок 2. Микроархитектура процессора._ 44: 000000000000 00100 001 01100 0000011 48: 000000000000 00100 000 01101 0000011 4C: 000000000000 00100 101 01110 0000011 -50: 000000000000 00100 100 11101 0000011 +50: 000000000000 00100 100 01111 0000011 54: 00000000000000000100 10000 0010111 58: 0000000 00011 00100 001 01000 1100011 5C: 00000000 00000000 00000000 00000000 From 667fa9d01a67b7461a68c5adc564bc69ea880973 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 2 Apr 2024 12:02:09 +0300 Subject: [PATCH 25/32] =?UTF-8?q?=D0=9B=D0=A06.=20=D0=94=D0=BE=D0=B1=D0=B0?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20hex-=D0=B7=D0=BD=D0=B0?= =?UTF-8?q?=D1=87=D0=B5=D0=BD=D0=B8=D0=B9=20=D0=B2=20=D0=B4=D0=B2=D0=BE?= =?UTF-8?q?=D0=B8=D1=87=D0=BD=D1=8B=D0=B9=20=D0=BB=D0=B8=D1=81=D1=82=D0=B8?= =?UTF-8?q?=D0=BD=D0=B3?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/06. Datapath/README.md | 54 ++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 27 deletions(-) diff --git a/Labs/06. Datapath/README.md b/Labs/06. Datapath/README.md index c250beb..93b5c83 100644 --- a/Labs/06. Datapath/README.md +++ b/Labs/06. Datapath/README.md @@ -139,33 +139,33 @@ _Рисунок 2. Микроархитектура процессора._ Теперь в соответствии с кодировкой инструкций переведем программу в машинные коды: ```text -00: 011101011100 00000 000 00001 0010011 -04: 100010100111 00000 000 00010 0010011 -08: 0000000 00010 00001 000 00011 0110011 -0C: 0000000 00010 00001 111 00100 0110011 -10: 0100000 00011 00100 000 00101 0110011 -14: 0000001 00100 00011 000 00110 0110011 -18: 00000101000000000000 01111 1101111 -1C: 000000000000 00110 000 01111 1100111 -20: 0000000 11111 00101 001 00111 0010011 -24: 0100000 00001 00111 101 01000 0010011 -28: 0000000 11101 01000 101 01001 0010011 -2C: 11111010110111101100 01010 0110111 -30: 101010111110 01010 000 01010 0010011 -34: 0000000 01010 00100 010 00000 0100011 -38: 0000000 01010 00100 001 00110 0100011 -3C: 0000000 01010 00100 000 01011 0100011 -40: 000000000000 00100 010 01011 0000011 -44: 000000000000 00100 001 01100 0000011 -48: 000000000000 00100 000 01101 0000011 -4C: 000000000000 00100 101 01110 0000011 -50: 000000000000 00100 100 01111 0000011 -54: 00000000000000000100 10000 0010111 -58: 0000000 00011 00100 001 01000 1100011 -5C: 00000000 00000000 00000000 00000000 -60: 00000000010000000000 10001 1101111 -64: 000000000000 10001 000 01110 1100111 -68: 000000000100 01111 000 10010 1100111 +00: 011101011100 00000 000 00001 0010011 (0x75C00093) +04: 100010100111 00000 000 00010 0010011 (0x8A700113) +08: 0000000 00010 00001 000 00011 0110011 (0x002081B3) +0C: 0000000 00010 00001 111 00100 0110011 (0x0020F233) +10: 0100000 00011 00100 000 00101 0110011 (0x403202B3) +14: 0000001 00100 00011 000 00110 0110011 (0x02418333) +18: 00000101000000000000 01111 1101111 (0x050007EF) +1C: 000000000000 00110 000 01111 1100111 (0x000307E7) +20: 0000000 11111 00101 001 00111 0010011 (0x01F29393) +24: 0100000 00001 00111 101 01000 0010011 (0x4013D413) +28: 0000000 11101 01000 101 01001 0010011 (0x01D45493) +2C: 11111010110111101100 01010 0110111 (0xFADEC537) +30: 101010111110 01010 000 01010 0010011 (0xABE50513) +34: 0000000 01010 00100 010 00000 0100011 (0x00A22023) +38: 0000000 01010 00100 001 00110 0100011 (0x00A21323) +3C: 0000000 01010 00100 000 01011 0100011 (0x00A205A3) +40: 000000000000 00100 010 01011 0000011 (0x00022583) +44: 000000000000 00100 001 01100 0000011 (0x00021603) +48: 000000000000 00100 000 01101 0000011 (0x00020683) +4C: 000000000000 00100 101 01110 0000011 (0x00025703) +50: 000000000000 00100 100 01111 0000011 (0x00024783) +54: 00000000000000000100 10000 0010111 (0x00004817) +58: 0000000 00011 00100 001 01000 1100011 (0x00321463) +5C: 00000000 00000000 00000000 00000000 (0x00000000) +60: 00000000010000000000 10001 1101111 (0x004008EF) +64: 000000000000 10001 000 01110 1100111 (0x00088767) +68: 000000000100 01111 000 10010 1100111 (0x00478967) ``` Данная программа, представленная в шестнадцатеричном формате находится в файле [program.mem](program.mem). From 13fca65559e6d90cdd8d8d2e857aee6ef44a04f2 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 2 Apr 2024 16:00:20 +0300 Subject: [PATCH 26/32] =?UTF-8?q?=D0=9B=D0=A04.=20=D0=98=D1=81=D0=BF=D1=80?= =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=B1=D0=B8=D1=82?= =?UTF-8?q?=D1=8B=D1=85=20=D1=81=D1=81=D1=8B=D0=BB=D0=BE=D0=BA?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit При переименовании файла в eacb727 не были исправлены ссылки на него. --- Labs/04. Primitive programmable device/README.md | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Labs/04. Primitive programmable device/README.md b/Labs/04. Primitive programmable device/README.md index 01632e9..8835c96 100644 --- a/Labs/04. Primitive programmable device/README.md +++ b/Labs/04. Primitive programmable device/README.md @@ -317,7 +317,7 @@ _Рисунок 5. Реализация безусловного переход Разработать процессор `CYBERcobra` (см. [_рис. 5_](../../.pic/Labs/lab_04_cybercobra/ppd_5.drawio.svg)), объединив ранее разработанные модули: -- Память инструкций (проинициализированную в двоичном формате файлом [`example.mem`](example.mem)) +- Память инструкций (проинициализированную в двоичном формате файлом [`program.mem`](program.mem)) - Регистровый файл - Арифметико-логическое устройство - 32-битный сумматор @@ -353,7 +353,7 @@ endmodule 5. Мультиплексор, выбирающий источник записи в регистровый файл. 3. После описания модуля, его необходимо проверить с помощью [`тестового окружения`](../../Basic%20Verilog%20structures/Testbench.md). 1. Тестовое окружение находится [`здесь`](tb_cybercobra.sv). - 2. Программа, которой необходимо проинициализировать память инструкций находится в файле [example.mem](example.mem). Алгоритм работы программы приведен в разделе [`Финальный обзор`](#финальный-обзор). + 2. Программа, которой необходимо проинициализировать память инструкций находится в файле [program.mem](program.mem). Алгоритм работы программы приведен в разделе [`Финальный обзор`](#финальный-обзор). 3. Для запуска симуляции воспользуйтесь [`этой инструкцией`](../../Vivado%20Basics/Run%20Simulation.md). 4. Перед запуском симуляции убедитесь, что выбран правильный модуль верхнего уровня. 5. **Во время симуляции, вы должны прожать "Run All" и убедиться, что в логе есть сообщение о завершении теста!** From 602230eb00d4c97aafd4649e7f975613d489a2ef Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Thu, 4 Apr 2024 15:01:50 +0300 Subject: [PATCH 27/32] =?UTF-8?q?=D0=9E=D0=B1=D0=BD=D0=BE=D0=B2=D0=BB?= =?UTF-8?q?=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BF=D1=80=D0=B5=D0=B7=D0=B5=D0=BD?= =?UTF-8?q?=D1=82=D0=B0=D1=86=D0=B8=D0=B9=20=D0=BB=D0=B5=D0=BA=D1=86=D0=B8?= =?UTF-8?q?=D0=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Lectures/Presentations | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Lectures/Presentations b/Lectures/Presentations index 480b999..c66b592 160000 --- a/Lectures/Presentations +++ b/Lectures/Presentations @@ -1 +1 @@ -Subproject commit 480b999cf20b7f8dc2454ee0bc70d86acabc143c +Subproject commit c66b5928fa695cc0f44cfd811b5d770c65eeecaa From 825674d1f9c13db7ad5b61fa5e80a04ec1623738 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 9 Apr 2024 14:38:31 +0300 Subject: [PATCH 28/32] =?UTF-8?q?=D0=9B=D0=A05.=20=D0=94=D0=BE=D0=B1=D0=B0?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BF=D0=BE=D1=8F=D1=81?= =?UTF-8?q?=D0=BD=D0=B5=D0=BD=D0=B8=D1=8F=20=D0=BF=D1=80=D0=BE=20=D0=BF?= =?UTF-8?q?=D0=BE=D0=BB=D0=B5=20shamt?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/05. Main decoder/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Labs/05. Main decoder/README.md b/Labs/05. Main decoder/README.md index d9ec20e..cf73843 100644 --- a/Labs/05. Main decoder/README.md +++ b/Labs/05. Main decoder/README.md @@ -77,7 +77,7 @@ SYSTEM-инструкции используются для доступа к с _Таблица 3. Инструкции набора RV32I с приведением их типов, функционального описания и примеров использования._ -Обратите внимание на операции `slli`, `srli` и `srai` (операции сдвига на константную величину). У этих инструкций немного измененный формат кодирования **I\***. Формат кодирования **I** предоставляет 12-битную константу. Сдвиг 32-битного числа более, чем на 31 не имеет смысла. Для кодирования числа 31 требуется всего 5 бит. Выходит, что из 12 бит константы используется только 5 бит для операции сдвига, а оставшиеся 7 бит – не используются. А, главное (какое совпадение!), эти 7 бит находятся ровно в том же месте, где у других инструкций находится поле `func7`. Поэтому, чтобы у инструкций `slli`, `srli` и `srai` использующих формат **I** не пропадала эта часть поля, к ней относятся как к полю `func7`. +Обратите внимание на операции `slli`, `srli` и `srai` (операции сдвига на константную величину). У этих инструкций немного измененный формат кодирования **I\***. Формат кодирования **I** предоставляет 12-битную константу. Сдвиг 32-битного числа более, чем на 31 не имеет смысла. Для кодирования числа 31 требуется всего 5 бит. Выходит, что из 12 бит константы используется только 5 бит для операции сдвига (в виде поля `shamt`, сокращение от **sh**ift **am**oun**t** — "сколько раз сдвигать"), а оставшиеся 7 бит – не используются. А, главное (какое совпадение!), эти 7 бит находятся ровно в том же месте, где у других инструкций находится поле `func7`. Поэтому, чтобы у инструкций `slli`, `srli` и `srai` использующих формат **I** не пропадала эта часть поля, к ней относятся как к полю `func7`. Также обратите внимание на инструкции `ecall`, `ebreak` и `mret`. Все эти инструкции I-типа имеют поле func3, равное нулю. С точки зрения декодирования инструкции I-типа, это одна и та же инструкция с разными полями. Однако конкретно в данном случае (SYSTEM_OPCODE и `func3 == 0`) эти инструкции должны рассматриваться как совокупность всех 32-бит сразу (см. _Таблицу 1_). From f98899de00d78081ac927dd17bc733e914b7f6e5 Mon Sep 17 00:00:00 2001 From: alexkharl Date: Tue, 9 Apr 2024 15:17:28 +0300 Subject: [PATCH 29/32] =?UTF-8?q?Feat(lab13/obf/uart=5Ftx):=D0=94=D0=BE?= =?UTF-8?q?=D0=B1-=D0=B8=D0=B5=20=D0=BE=D0=B1=D1=84=20uart=5Ftx=5Fsb=5Fctr?= =?UTF-8?q?l?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../Made-up modules/lab_13.uart_tx_sb_ctrl.sv | 715 +++++++++++++++++- 1 file changed, 714 insertions(+), 1 deletion(-) diff --git a/Labs/Made-up modules/lab_13.uart_tx_sb_ctrl.sv b/Labs/Made-up modules/lab_13.uart_tx_sb_ctrl.sv index 9bd0d0f..83e2d51 100644 --- a/Labs/Made-up modules/lab_13.uart_tx_sb_ctrl.sv +++ b/Labs/Made-up modules/lab_13.uart_tx_sb_ctrl.sv @@ -1,4 +1,717 @@ -module uart_tx_sb_ctrl(); +module uart_tx_sb_ctrl( +/* + Часть интерфейса модуля, отвечающая за подключение к системной шине +*/ + input logic clk_i, + input logic rst_i, + input logic [31:0] addr_i, + input logic req_i, + input logic [31:0] write_data_i, + input logic write_enable_i, + output logic [31:0] read_data_o, +/* + Часть интерфейса модуля, отвечающая за подключение передающему, + входные данные по UART +*/ + output logic tx_o +); + logic busy; + logic [16:0] baudrate; + logic fcS5S0IailtPh; + logic parity_en; + logic stopbit; + logic [7:0] data; + logic valid; + logic wKSnwVGWV, eY8BfVPWv; + + logic qICjuvAOmWmr; + assign qICjuvAOmWmr = write_enable_i; + logic [31:0] UmLX; + assign UmLX = addr_i; + logic [31:0] FFDK4sD9m7; + assign FFDK4sD9m7 = write_data_i; + logic zZF; + assign zZF = rst_i; + logic [31:0] X5ldx3X4a; + assign read_data_o = X5ldx3X4a; + logic q0MK89N8qKhS8mdymRsz; + + logic VICULOkZm; + + logic r0UH06pov5; + uart_tx Ou( + .clk_i (clk_i), + .rst_i (zZF), + .tx_o (tx_o), + .busy_o (eY8BfVPWv), + .baudrate_i (baudrate), + .parity_en_i(parity_en), + .stopbit_i (stopbit), + .tx_data_i (data), + .tx_valid_i (valid) + ); + logic pEo; + + logic [31:0] vJlF3gash; + always_comb begin + case ({valid, wKSnwVGWV, valid, VICULOkZm, XJhsywc8r, eY8BfVPWv, q0MK89N8qKhS8mdymRsz}) + 7'b1100011: vJlF3gash = 32'd10945 ^ 32'o25300; + 7'h77: vJlF3gash = 32'd17511 ^ 32'h4466; + 7'ha: vJlF3gash = 32'o45111 ^ 32'h4a48; + 7'b1001100: vJlF3gash = 32'b00000000000000000001001100100110 ^ 32'o11447; + 7'h75: vJlF3gash = 32'b00000000000000000111000001101111 ^ 32'o44127 ^ 32'o34071; + 7'b1111111: vJlF3gash = 32'o64103 ^ 32'o64103; + 7'o21: vJlF3gash = 32'b00000000000000000001101000101100 ^ 32'd6701; + 7'h29: vJlF3gash = 32'd1472 ^ 32'b00000000000000000000010111000000; + 7'h69: vJlF3gash = 32'o75244 ^ 32'h7aa5; + 7'o40: vJlF3gash = 32'o33750 ^ 32'b00000000000000000011011111101000; + 7'o106: vJlF3gash = 32'o66477 ^ 32'o66476; + 7'o146: vJlF3gash = 32'd21171 ^ 32'h1a7c ^ 32'o44316; + 7'h4a: vJlF3gash = 32'b00000000000000000011111100101101 ^ 32'b00000000000000000011111100101100; + 7'd78: vJlF3gash = 32'd4379 ^ 32'd4378; + 7'o7: vJlF3gash = 32'd8791 ^ 32'd13824 ^ 32'b00000000000000000001010001010110; + 7'd57: vJlF3gash = 32'h4d78 ^ 32'd7290 ^ 32'd20739; + 7'd53: vJlF3gash = 32'h7b8a ^ 32'b00000000000000000011111110010010 ^ 32'o42031; + 7'o140: vJlF3gash = 32'd11468 ^ 32'd11469; + 7'o24: vJlF3gash = 32'h421e ^ 32'h1283 ^ 32'o50234; + 7'o33: vJlF3gash = 32'b00000000000000000011101111111101 ^ 32'h68c ^ 32'b00000000000000000011110101110000; + 7'd52: vJlF3gash = 32'o50616 ^ 32'o50617; + 7'h33: vJlF3gash = 32'o23622 ^ 32'o23623; + 7'o104: vJlF3gash = 32'o67512 ^ 32'd28491; + 7'd48: vJlF3gash = 32'h7fa0 ^ 32'b00000000000000000001110011100001 ^ 32'o61500; + 7'd65: vJlF3gash = 32'h7155 ^ 32'b00000000000000000111000101010100; + 7'h70: vJlF3gash = 32'b00000000000000000111010010000100 ^ 32'b00000000000000000010010110100110 ^ 32'o50443; + 7'd2: vJlF3gash = 32'd9837 ^ 32'h134f ^ 32'o32443; + 7'd24: vJlF3gash = 32'o12014 ^ 32'o67553 ^ 32'd31590; + 7'b0001100: vJlF3gash = 32'o17102 ^ 32'd7746; + 7'b0010110: vJlF3gash = 32'b00000000000000000100000000010011 ^ 32'h63db ^ 32'b00000000000000000010001111001001; + 7'd0: vJlF3gash = 32'h5274 ^ 32'd1982 ^ 32'h55ca; + 7'd49: vJlF3gash = 32'd10652 ^ 32'o61251 ^ 32'h4b34; + 7'o121: vJlF3gash = 32'd3856 ^ 32'o7421; + 7'b0010010: vJlF3gash = 32'o67045 ^ 32'd1778 ^ 32'h68d6; + 7'd69: vJlF3gash = 32'o41503 ^ 32'b00000000000000000100001101000010; + 7'd91: vJlF3gash = 32'b00000000000000000011000011100010 ^ 32'h30e3; + 7'h6: vJlF3gash = 32'h785b ^ 32'h785a; + 7'b1001000: vJlF3gash = 32'b00000000000000000100000100111000 ^ 32'h4139; + 7'b1011101: vJlF3gash = 32'b00000000000000000000010011011010 ^ 32'h1ae2 ^ 32'd7737; + 7'b0001001: vJlF3gash = 32'o20114 ^ 32'd1880 ^ 32'b00000000000000000010011100010100; + 7'd77: vJlF3gash = 32'd15650 ^ 32'h3d23; + 7'h37: vJlF3gash = 32'b00000000000000000100111110000011 ^ 32'b00000000000000000100111110000010; + 7'o52: vJlF3gash = 32'o54671 ^ 32'h3467 ^ 32'b00000000000000000110110111011111; + 7'o44: vJlF3gash = 32'b00000000000000000000100111010110 ^ 32'b00000000000000000000100111010110; + 7'o145: vJlF3gash = 32'h28b6 ^ 32'd10423; + 7'h49: vJlF3gash = 32'd27444 ^ 32'h4a56 ^ 32'd8547; + 7'o154: vJlF3gash = 32'o21226 ^ 32'o44275 ^ 32'd27178; + 7'b0000011: vJlF3gash = 32'b00000000000000000101000001101001 ^ 32'b00000000000000000101100100010111 ^ 32'h97f; + 7'd5: vJlF3gash = 32'd20062 ^ 32'h4e5e; + 7'd106: vJlF3gash = 32'd9377 ^ 32'o73545 ^ 32'd21445; + 7'b0001000: vJlF3gash = 32'h4c54 ^ 32'b00000000000000000100110001010100; + 7'd38: vJlF3gash = 32'd1995 ^ 32'h7ca; + 7'h28: vJlF3gash = 32'd23492 ^ 32'o61417 ^ 32'b00000000000000000011100011001011; + 7'b1010100: vJlF3gash = 32'b00000000000000000011011100000010 ^ 32'h1b48 ^ 32'o26113; + 7'd103: vJlF3gash = 32'o23254 ^ 32'b00000000000000000010011000001100 ^ 32'd161; + 7'b0110010: vJlF3gash = 32'o51631 ^ 32'd21400; + 7'b0101011: vJlF3gash = 32'h3b6 ^ 32'h3b7; + 7'd26: vJlF3gash = 32'b00000000000000000001001000000001 ^ 32'o40304 ^ 32'd21188; + 7'h1f: vJlF3gash = 32'b00000000000000000000110111101011 ^ 32'h6375 ^ 32'h6e9f; + 7'h3e: vJlF3gash = 32'h4963 ^ 32'b00000000000000000011111100101011 ^ 32'd30281; + 7'd98: vJlF3gash = 32'b00000000000000000000000011000101 ^ 32'd15763 ^ 32'd15703; + 7'o132: vJlF3gash = 32'o56351 ^ 32'o56350; + 7'h21: vJlF3gash = 32'o60744 ^ 32'b00000000000000000110111100000101 ^ 32'o7341; + 7'h1: vJlF3gash = 32'd31856 ^ 32'h7c70; + 7'h50: vJlF3gash = 32'o62424 ^ 32'd15967 ^ 32'd23370; + 7'o56: vJlF3gash = 32'h1ab ^ 32'b00000000000000000000000110101010; + 7'd56: vJlF3gash = 32'b00000000000000000010001101111100 ^ 32'o21575; + 7'o107: vJlF3gash = 32'o13473 ^ 32'd16069 ^ 32'o24777; + 7'h1e: vJlF3gash = 32'o61757 ^ 32'd25582; + 7'd58: vJlF3gash = 32'h7775 ^ 32'o61103 ^ 32'b00000000000000000001010100110111; + 7'h19: vJlF3gash = 32'h6805 ^ 32'd26628; + 7'o176: vJlF3gash = 32'b00000000000000000011111001000111 ^ 32'b00000000000000000100011111110001 ^ 32'd31159; + 7'b0101111: vJlF3gash = 32'h55a4 ^ 32'o52644; + 7'h43: vJlF3gash = 32'h454d ^ 32'b00000000000000000110000111011101 ^ 32'h2491; + 7'd121: vJlF3gash = 32'b00000000000000000100001001011101 ^ 32'b00000000000000000010010101000000 ^ 32'd26396; + 7'd23: vJlF3gash = 32'd27151 ^ 32'o65016; + 7'hf: vJlF3gash = 32'b00000000000000000100011000110011 ^ 32'h4632; + 7'b1110100: vJlF3gash = 32'd7286 ^ 32'd7287; + 7'h58: vJlF3gash = 32'b00000000000000000000100011110000 ^ 32'o74061 ^ 32'd28864; + 7'h7b: vJlF3gash = 32'h1655 ^ 32'o13124; + 7'o55: vJlF3gash = 32'h57ae ^ 32'd22446; + 7'o127: vJlF3gash = 32'o57363 ^ 32'd24306; + 7'o13: vJlF3gash = 32'h7445 ^ 32'h12e9 ^ 32'd26285; + 7'd60: vJlF3gash = 32'd30058 ^ 32'b00000000000000000111010101101011; + 7'd104: vJlF3gash = 32'o50250 ^ 32'h6bd4 ^ 32'o35575; + 7'h73: vJlF3gash = 32'h7279 ^ 32'b00000000000000000111011011111111 ^ 32'o2207; + 7'd107: vJlF3gash = 32'd20125 ^ 32'h3d2d ^ 32'o71661; + 7'b1001111: vJlF3gash = 32'd15127 ^ 32'b00000000000000000011101100010110; + 7'h1d: vJlF3gash = 32'hff6 ^ 32'o11034 ^ 32'd7659; + 7'b1010011: vJlF3gash = 32'hd05 ^ 32'b00000000000000000000110100000100; + 7'o122: vJlF3gash = 32'd25353 ^ 32'd4024 ^ 32'h6cb0; + 7'd39: vJlF3gash = 32'h31c8 ^ 32'b00000000000000000001110101000111 ^ 32'd11406; + 7'h36: vJlF3gash = 32'b00000000000000000010010110000111 ^ 32'd9606; + 7'h1c: vJlF3gash = 32'h65fa ^ 32'o62773; + 7'o170: vJlF3gash = 32'h6e64 ^ 32'o14660 ^ 32'o73725; + 7'd63: vJlF3gash = 32'h735f ^ 32'h735f; + 7'o125: vJlF3gash = 32'h60fe ^ 32'o60377; + 7'd19: vJlF3gash = 32'b00000000000000000001100000100001 ^ 32'o14040; + 7'd125: vJlF3gash = 32'o65116 ^ 32'd27214; + 7'b1101111: vJlF3gash = 32'd8331 ^ 32'o15026 ^ 32'd15005; + 7'o25: vJlF3gash = 32'd5655 ^ 32'd5654; + 7'o16: vJlF3gash = 32'o16067 ^ 32'o16066; + 7'h6d: vJlF3gash = 32'o46222 ^ 32'h4c92; + 7'o161: vJlF3gash = 32'o17201 ^ 32'h6b6e ^ 32'd30190; + 7'b0010000: vJlF3gash = 32'd28720 ^ 32'd13722 ^ 32'h45ab; + 7'b1001011: vJlF3gash = 32'o64451 ^ 32'd7086 ^ 32'd29318; + 7'h22: vJlF3gash = 32'b00000000000000000011010111011101 ^ 32'h35dc; + 7'b1101110: vJlF3gash = 32'b00000000000000000111011010001111 ^ 32'h768e; + 7'o141: vJlF3gash = 32'd22216 ^ 32'o73713 ^ 32'o20402; + 7'o102: vJlF3gash = 32'o15521 ^ 32'd7188 ^ 32'o3504; + 7'o54: vJlF3gash = 32'd11698 ^ 32'b00000000000000000011111111111000 ^ 32'd4682; + 7'd100: vJlF3gash = 32'h7eba ^ 32'h7ebb; + 7'd94: vJlF3gash = 32'b00000000000000000010111011010111 ^ 32'b00000000000000000010111011010110; + 7'd37: vJlF3gash = 32'b00000000000000000011001111010010 ^ 32'b00000000000000000011001111010010; + 7'b0111101: vJlF3gash = 32'd8038 ^ 32'o17546; + 7'b1110010: vJlF3gash = 32'b00000000000000000100100001111101 ^ 32'h487c; + 7'b0111011: vJlF3gash = 32'd8561 ^ 32'd8560; + 7'd92: vJlF3gash = 32'b00000000000000000101101011011110 ^ 32'd23263; + 7'd4: vJlF3gash = 32'o22142 ^ 32'd25767 ^ 32'b00000000000000000100000011000101; + 7'd89: vJlF3gash = 32'b00000000000000000011001011101100 ^ 32'd15865 ^ 32'o7424; + 7'b1110110: vJlF3gash = 32'd6763 ^ 32'o15152; + 7'b1000000: vJlF3gash = 32'd7516 ^ 32'd19132 ^ 32'o53741; + 7'b1010110: vJlF3gash = 32'hafb ^ 32'hafa; + 7'hd: vJlF3gash = 32'o71073 ^ 32'h6441 ^ 32'h167a; + 7'h5f: vJlF3gash = 32'b00000000000000000101100011010011 ^ 32'o54322; + 7'b1111100: vJlF3gash = 32'h4052 ^ 32'b00000000000000000111011010011001 ^ 32'd14026; + 7'd35: vJlF3gash = 32'd24537 ^ 32'o40136 ^ 32'o17606; + 7'd122: vJlF3gash = 32'b00000000000000000110110001011001 ^ 32'o65410 ^ 32'o3520; + endcase + end + + logic [31:0] qaz6wx1C86; + + always_ff @(posedge clk_i) begin + if(zZF) begin + busy <= '0; + end else begin + busy <= vJlF3gash[32'b00000000000000000110010010101011 ^ 32'd21989 ^ 32'o30516]; + end + end + + logic [31:0] q5Upj3TRGS8nkfV; + always_comb begin + case ({wKSnwVGWV, VICULOkZm, valid, eY8BfVPWv, XJhsywc8r, r0UH06pov5}) + 6'd57: qaz6wx1C86 = 32'b00000000000000000100110110100011 ^ 32'd5756 ^ 32'b00000000000000000101101111011110; + 6'o32: qaz6wx1C86 = 32'h122b ^ 32'o35305 ^ 32'd10478; + 6'o70: qaz6wx1C86 = 32'h23a6 ^ 32'd9126; + 6'h17: qaz6wx1C86 = 32'b00000000000000000001010000110110 ^ 32'o64555 ^ 32'b00000000000000000111110101011011; + 6'd48: qaz6wx1C86 = 32'b00000000000000000111111111001010 ^ 32'b00000000000000000001011011100010 ^ 32'h6928; + 6'b100010: qaz6wx1C86 = 32'b00000000000000000011011000000111 ^ 32'd29847 ^ 32'b00000000000000000100001010010000; + 6'b101000: qaz6wx1C86 = 32'h5eb ^ 32'h5eb; + 6'o34: qaz6wx1C86 = 32'b00000000000000000001000000100001 ^ 32'o6036 ^ 32'd7231; + 6'd17: qaz6wx1C86 = 32'h4453 ^ 32'o35453 ^ 32'o77570; + 6'h3b: qaz6wx1C86 = 32'h4b98 ^ 32'b00000000000000000110011111010100 ^ 32'b00000000000000000010110001001100; + 6'o25: qaz6wx1C86 = 32'h1641 ^ 32'o14024 ^ 32'b00000000000000000000111001010101; + 6'o44: qaz6wx1C86 = 32'd13309 ^ 32'b00000000000000000100010111110000 ^ 32'b00000000000000000111011000001101; + 6'h27: qaz6wx1C86 = 32'o30762 ^ 32'b00000000000000000001011101001000 ^ 32'b00000000000000000010011010111011; + 6'o41: qaz6wx1C86 = 32'd3083 ^ 32'b00000000000000000000110000001010; + 6'o23: qaz6wx1C86 = 32'b00000000000000000100001001001000 ^ 32'hc84 ^ 32'o47314; + 6'd29: qaz6wx1C86 = 32'b00000000000000000011101000011101 ^ 32'b00000000000000000011101000011101; + 6'd32: qaz6wx1C86 = 32'd25103 ^ 32'o64407 ^ 32'hb08; + 6'o74: qaz6wx1C86 = 32'o72624 ^ 32'h7594; + 6'b101001: qaz6wx1C86 = 32'd12263 ^ 32'b00000000000000000110100010100001 ^ 32'b00000000000000000100011101000111; + 6'o17: qaz6wx1C86 = 32'd28762 ^ 32'o70132; + 6'd53: qaz6wx1C86 = 32'b00000000000000000111101110110101 ^ 32'b00000000000000000011100110010011 ^ 32'o41047; + 6'h10: qaz6wx1C86 = 32'd6743 ^ 32'o15127; + 6'b000100: qaz6wx1C86 = 32'd9356 ^ 32'd24233 ^ 32'o75045; + 6'b010100: qaz6wx1C86 = 32'h6c45 ^ 32'o66105; + 6'b111111: qaz6wx1C86 = 32'o16606 ^ 32'd17597 ^ 32'h593b; + 6'd42: qaz6wx1C86 = 32'o54744 ^ 32'd23012; + 6'b011000: qaz6wx1C86 = 32'o37063 ^ 32'b00000000000000000011111000110011; + 6'b101111: qaz6wx1C86 = 32'b00000000000000000101010111001110 ^ 32'd21967; + 6'b111110: qaz6wx1C86 = 32'b00000000000000000100100110001101 ^ 32'b00000000000000000011100100101101 ^ 32'd28832; + 6'o62: qaz6wx1C86 = 32'h7dc0 ^ 32'b00000000000000000110100000111010 ^ 32'h15fa; + 6'o53: qaz6wx1C86 = 32'b00000000000000000000001111100000 ^ 32'd29745 ^ 32'h77d0; + 6'o16: qaz6wx1C86 = 32'd7265 ^ 32'd7265; + 6'b011111: qaz6wx1C86 = 32'd14354 ^ 32'h3812; + 6'h9: qaz6wx1C86 = 32'b00000000000000000010000001110111 ^ 32'd8311; + 6'b100101: qaz6wx1C86 = 32'd24057 ^ 32'o5670 ^ 32'o53100; + 6'h1: qaz6wx1C86 = 32'h7c9b ^ 32'b00000000000000000111110010011011; + 6'h12: qaz6wx1C86 = 32'h6e4f ^ 32'd28239; + 6'o66: qaz6wx1C86 = 32'h4fae ^ 32'd17699 ^ 32'b00000000000000000000101010001101; + 6'o2: qaz6wx1C86 = 32'h5094 ^ 32'h5094; + 6'h8: qaz6wx1C86 = 32'd30330 ^ 32'h3b92 ^ 32'b00000000000000000100110111101000; + 6'd51: qaz6wx1C86 = 32'd10172 ^ 32'd10172; + 6'b101100: qaz6wx1C86 = 32'o26734 ^ 32'b00000000000000000011100111111001 ^ 32'd5157; + 6'h34: qaz6wx1C86 = 32'b00000000000000000101000110111000 ^ 32'd29643 ^ 32'b00000000000000000010001001110011; + 6'd55: qaz6wx1C86 = 32'h79aa ^ 32'h79aa; + 6'b010110: qaz6wx1C86 = 32'h403d ^ 32'h403d; + 6'b111101: qaz6wx1C86 = 32'd8081 ^ 32'h7365 ^ 32'h6cf5; + 6'd27: qaz6wx1C86 = 32'd26148 ^ 32'b00000000000000000100011001010110 ^ 32'h2072; + 6'h7: qaz6wx1C86 = 32'o46176 ^ 32'h4c7e; + 6'h2e: qaz6wx1C86 = 32'b00000000000000000010101111010010 ^ 32'd11218; + 6'o5: qaz6wx1C86 = 32'o47211 ^ 32'b00000000000000000100111010001001; + 6'o55: qaz6wx1C86 = 32'h1d5 ^ 32'd17801 ^ 32'h445d; + 6'b000110: qaz6wx1C86 = 32'b00000000000000000111100010000101 ^ 32'o65071 ^ 32'b00000000000000000001001010111100; + 6'd25: qaz6wx1C86 = 32'o64057 ^ 32'o64057; + 6'd11: qaz6wx1C86 = 32'b00000000000000000001111001101100 ^ 32'o17154; + 6'o72: qaz6wx1C86 = 32'o20634 ^ 32'h220c ^ 32'h390; + 6'd35: qaz6wx1C86 = 32'o60004 ^ 32'o35137 ^ 32'o55132; + 6'h3: qaz6wx1C86 = 32'h7a90 ^ 32'o14341 ^ 32'b00000000000000000110001001110001; + 6'h0: qaz6wx1C86 = 32'h529e ^ 32'b00000000000000000101001010011110; + 6'o14: qaz6wx1C86 = 32'h4869 ^ 32'o14172 ^ 32'h5013; + 6'd49: qaz6wx1C86 = 32'b00000000000000000101001111000011 ^ 32'h53c2; + 6'o12: qaz6wx1C86 = 32'b00000000000000000100101001110011 ^ 32'b00000000000000000100101001110011; + 6'b100110: qaz6wx1C86 = 32'h7f6 ^ 32'b00000000000000000000011111110110; + 6'd13: qaz6wx1C86 = 32'd29285 ^ 32'h5e43 ^ 32'd11302; + 6'b011110: qaz6wx1C86 = 32'o62031 ^ 32'b00000000000000000001011110101110 ^ 32'h73b7; + endcase + end + + assign r0UH06pov5 = UmLX == (32'o32572 ^ 32'h357a); + + always_ff @(posedge clk_i) begin + if(zZF) begin + valid <= '0; + end else begin + valid <= qaz6wx1C86[32'o46742 ^ 32'o24471 ^ 32'h64db]; + end + end + + logic VVZKlkqbq; + assign VVZKlkqbq = UmLX == (32'h73e2 ^ 32'b00000000000000000001101001001000 ^ 32'o64652); + always_comb begin + case ({wKSnwVGWV, VICULOkZm, VVZKlkqbq, XJhsywc8r}) + 4'b1101: q5Upj3TRGS8nkfV = 32'h5ea0 ^ 32'hed25493; + 4'd3: q5Upj3TRGS8nkfV = 32'd15044 ^ 32'h3f17 ^ 32'b01011110010110011010111010001111; + 4'h6: q5Upj3TRGS8nkfV = 32'o34271 ^ 32'd4207 ^ 32'd832212430; + 4'o13: q5Upj3TRGS8nkfV = 32'o5247 ^ 32'h6d58 ^ 32'h6f961b2b; + 4'h0: q5Upj3TRGS8nkfV = 32'b00000000000000000001001011010010 ^ 32'o14336040213; + 4'd7: q5Upj3TRGS8nkfV = 32'd25270 ^ 32'h1bc519ae; + 4'o4: q5Upj3TRGS8nkfV = 32'd25792 ^ 32'b01010100100001001010111011011101; + 4'ha: q5Upj3TRGS8nkfV = 32'h60ab ^ 32'b00011110001100100000110100000110; + 4'hc: q5Upj3TRGS8nkfV = 32'h34a4 ^ 32'd13088 ^ 32'd102164953; + 4'o2: q5Upj3TRGS8nkfV = 32'b00000000000000000001000011001000 ^ 32'd1470131080; + 4'd5: q5Upj3TRGS8nkfV = 32'd3773 ^ 32'o14677436470; + 4'o17: q5Upj3TRGS8nkfV = 32'o31231 ^ 32'b01100100111110100100110000011011; + 4'b0001: q5Upj3TRGS8nkfV = 32'o36317 ^ 32'h6dbe ^ 32'b01010001100000101111011101101001; + 4'h8: q5Upj3TRGS8nkfV = 32'd3250 ^ 32'h1c00 ^ 32'h42d7eb62; + 4'b1110: q5Upj3TRGS8nkfV = 32'd2205 ^ 32'h3eb1 ^ 32'h74c58ad8; + 4'd9: q5Upj3TRGS8nkfV = 32'd13999 ^ 32'd25032 ^ 32'd1908358519; + endcase + end + + logic [31:0] eBnHjxu3POlmkT7; + assign XJhsywc8r = FFDK4sD9m7 == (32'o26420 ^ 32'b00000000000000000011010010011010 ^ 32'h198b); + always_comb begin + case ({wKSnwVGWV, VICULOkZm, VVZKlkqbq, XJhsywc8r}) + 4'd13: eBnHjxu3POlmkT7 = 32'o62772 ^ 32'd25234 ^ 32'd619253058; + 4'h9: eBnHjxu3POlmkT7 = 32'o37011 ^ 32'h78b64f90; + 4'h5: eBnHjxu3POlmkT7 = 32'd5655 ^ 32'd13393 ^ 32'o14774560176; + 4'b0011: eBnHjxu3POlmkT7 = 32'h421e ^ 32'o24300 ^ 32'h33beeb7f; + 4'b1110: eBnHjxu3POlmkT7 = 32'hff7 ^ 32'b00000000000000000010100001011010 ^ 32'b01111101110010100011111011111010; + 4'h7: eBnHjxu3POlmkT7 = 32'o65020 ^ 32'o16034426322; + 4'b0100: eBnHjxu3POlmkT7 = 32'h6c1b ^ 32'd1616384739; + 4'd15: eBnHjxu3POlmkT7 = 32'b00000000000000000011100111110011 ^ 32'h6d8d37c6; + 4'h2: eBnHjxu3POlmkT7 = 32'o14042 ^ 32'd25336 ^ 32'o2654636133; + 4'b0110: eBnHjxu3POlmkT7 = 32'b00000000000000000100000000010100 ^ 32'o75031 ^ 32'h1a1b1874; + 4'b0001: eBnHjxu3POlmkT7 = 32'b00000000000000000100010000101001 ^ 32'b00000000000000000101011101101000 ^ 32'h2ef4b8b3; + 4'd8: eBnHjxu3POlmkT7 = 32'h140c ^ 32'b00000000000000000000010110101001 ^ 32'b01101100000110101011001000011111; + 4'hb: eBnHjxu3POlmkT7 = 32'b00000000000000000001001000000010 ^ 32'b00000000000000000101011100000010 ^ 32'b00101111110001001001110111011101; + 4'b1010: eBnHjxu3POlmkT7 = 32'o64005 ^ 32'd1843325073; + 4'h0: eBnHjxu3POlmkT7 = 32'h1a2d ^ 32'd734609828; + 4'd12: eBnHjxu3POlmkT7 = 32'b00000000000000000011101111111110 ^ 32'b01110001100110001001111110011100; + endcase + end + + always_ff @(posedge clk_i) begin + if(zZF) begin + data <= '0; + end else if (q5Upj3TRGS8nkfV[32'd23241 ^ 32'b00000000000000000101101011001000]) begin + data <= '0; + end else if(eBnHjxu3POlmkT7[32'o72553 ^ 32'b00000000000000000111010101101001]) begin + data <= FFDK4sD9m7; + end + else begin + data <= data; + end + end + + assign fcS5S0IailtPh = UmLX == (32'o13330 ^ 32'o43045 ^ 32'd20721); + logic [31:0] SuhrzWcGiwP2SmTaYCK; + always_comb begin + case ({wKSnwVGWV, fcS5S0IailtPh, VICULOkZm, XJhsywc8r}) + 4'd5: SuhrzWcGiwP2SmTaYCK = 32'h664e ^ 32'o31120 ^ 32'h121a79bb; + 4'h4: SuhrzWcGiwP2SmTaYCK = 32'h3c52 ^ 32'o16325204045; + 4'h1: SuhrzWcGiwP2SmTaYCK = 32'd15965 ^ 32'd2111526847; + 4'd13: SuhrzWcGiwP2SmTaYCK = 32'd13874 ^ 32'b00000000000000000110000010010010 ^ 32'b01111110111010011111001101110001; + 4'd8: SuhrzWcGiwP2SmTaYCK = 32'b00000000000000000110010001000100 ^ 32'o1651 ^ 32'h39cc7d3b; + 4'hc: SuhrzWcGiwP2SmTaYCK = 32'o6065 ^ 32'd343741462; + 4'b1011: SuhrzWcGiwP2SmTaYCK = 32'h6239 ^ 32'h5501 ^ 32'o6775127066; + 4'd10: SuhrzWcGiwP2SmTaYCK = 32'o34075 ^ 32'o6174646137; + 4'd3: SuhrzWcGiwP2SmTaYCK = 32'b00000000000000000001001001010110 ^ 32'h26c0 ^ 32'd368251297; + 4'd2: SuhrzWcGiwP2SmTaYCK = 32'h6859 ^ 32'b00000110101101000010000000111010; + 4'o7: SuhrzWcGiwP2SmTaYCK = 32'h3a47 ^ 32'd1161903040; + 4'he: SuhrzWcGiwP2SmTaYCK = 32'b00000000000000000000101000101011 ^ 32'o17563345053; + 4'h9: SuhrzWcGiwP2SmTaYCK = 32'o7100 ^ 32'o15764422501; + 4'o6: SuhrzWcGiwP2SmTaYCK = 32'd4171 ^ 32'd30744 ^ 32'd6904852; + 4'd15: SuhrzWcGiwP2SmTaYCK = 32'o32047 ^ 32'o30752 ^ 32'b01110010010101100100010111100000; + 4'd0: SuhrzWcGiwP2SmTaYCK = 32'h1460 ^ 32'h5567 ^ 32'd882296647; + endcase + end + + logic [31:0] FHGBch0qBHxqcbX8Dlb; + always_comb begin + case ({wKSnwVGWV, fcS5S0IailtPh, VICULOkZm, XJhsywc8r}) + 4'd12: FHGBch0qBHxqcbX8Dlb = 32'b00000000000000000000110001001011 ^ 32'h331f09ba; + 4'd15: FHGBch0qBHxqcbX8Dlb = 32'd2624 ^ 32'b00111010001111100110100101010111; + 4'd0: FHGBch0qBHxqcbX8Dlb = 32'h6a79 ^ 32'o11016714577; + 4'h4: FHGBch0qBHxqcbX8Dlb = 32'o36147 ^ 32'b00000110001011010101001100101101; + 4'd14: FHGBch0qBHxqcbX8Dlb = 32'd24643 ^ 32'h635a ^ 32'h36813882; + 4'ha: FHGBch0qBHxqcbX8Dlb = 32'b00000000000000000011100001010010 ^ 32'b00000000000000000100110000111010 ^ 32'o2211317713; + 4'b1011: FHGBch0qBHxqcbX8Dlb = 32'o61116 ^ 32'h1202 ^ 32'h21745a02; + 4'o2: FHGBch0qBHxqcbX8Dlb = 32'd26734 ^ 32'o16770 ^ 32'h4fc6d1d5; + 4'b0101: FHGBch0qBHxqcbX8Dlb = 32'o63144 ^ 32'o67521 ^ 32'h714246f3; + 4'b0110: FHGBch0qBHxqcbX8Dlb = 32'o10140 ^ 32'h427bb924; + 4'h1: FHGBch0qBHxqcbX8Dlb = 32'o12166 ^ 32'h1268 ^ 32'b01101001010000011001010010110110; + 4'd13: FHGBch0qBHxqcbX8Dlb = 32'h3647 ^ 32'o16622 ^ 32'b01110110001010000111000100101100; + 4'h9: FHGBch0qBHxqcbX8Dlb = 32'b00000000000000000000111001010101 ^ 32'b01001011011110100011011100111100; + 4'h7: FHGBch0qBHxqcbX8Dlb = 32'o35134 ^ 32'h459eecf4; + 4'h8: FHGBch0qBHxqcbX8Dlb = 32'd25689 ^ 32'o40251 ^ 32'h3a6f4fd0; + 4'o3: FHGBch0qBHxqcbX8Dlb = 32'd4715 ^ 32'h63c1 ^ 32'b01001111110001011111010111000100; + endcase + end + + always_ff @(posedge clk_i) begin + if(zZF) begin + baudrate <= '0; + end else if (SuhrzWcGiwP2SmTaYCK[32'd3188 ^ 32'b00000000000000000000110001110111]) begin + baudrate <= '0; + end + else if(FHGBch0qBHxqcbX8Dlb[32'b00000000000000000000110101101111 ^ 32'h787d ^ 32'o72426]) begin + baudrate <= FFDK4sD9m7; + end + else begin + baudrate <= baudrate; + end + end + + logic [31:0] WLGbSSV5YzHmlpmqLI; + + logic [31:0] b5l5UfftZRDTX1AD2; + logic m4Js9aFV4Us; + always_comb begin + case ({wKSnwVGWV, m4Js9aFV4Us, VICULOkZm, XJhsywc8r}) + 4'd14: b5l5UfftZRDTX1AD2 = 32'b00000000000000000110010110000000 ^ 32'd295811877; + 4'b0111: b5l5UfftZRDTX1AD2 = 32'h159d ^ 32'o12602005631; + 4'd6: b5l5UfftZRDTX1AD2 = 32'h6ba0 ^ 32'o11557450265; + 4'd2: b5l5UfftZRDTX1AD2 = 32'h43af ^ 32'd17152 ^ 32'h22f4f996; + 4'b1101: b5l5UfftZRDTX1AD2 = 32'b00000000000000000011101110000100 ^ 32'h1e89d3c; + 4'o13: b5l5UfftZRDTX1AD2 = 32'o63613 ^ 32'o15557237564; + 4'd1: b5l5UfftZRDTX1AD2 = 32'd6578 ^ 32'o2423507117; + 4'b1111: b5l5UfftZRDTX1AD2 = 32'b00000000000000000000111101111101 ^ 32'd5106 ^ 32'b00101010110111011010011011110000; + 4'h4: b5l5UfftZRDTX1AD2 = 32'h17a8 ^ 32'd1199459581; + 4'o5: b5l5UfftZRDTX1AD2 = 32'b00000000000000000100000110100100 ^ 32'b00000000000000000001010001011000 ^ 32'h2acd6c79; + 4'd3: b5l5UfftZRDTX1AD2 = 32'h6dab ^ 32'd2104322542; + 4'o10: b5l5UfftZRDTX1AD2 = 32'o64626 ^ 32'd407919674; + 4'b1100: b5l5UfftZRDTX1AD2 = 32'h1187 ^ 32'd17050 ^ 32'b00100101100100001010000100001000; + 4'h9: b5l5UfftZRDTX1AD2 = 32'd5010 ^ 32'd28993 ^ 32'b01000000000011010011100101100111; + 4'b0000: b5l5UfftZRDTX1AD2 = 32'o67666 ^ 32'o33557 ^ 32'd1228297272; + 4'o12: b5l5UfftZRDTX1AD2 = 32'b00000000000000000011110110001110 ^ 32'b00000000000000000011011100001001 ^ 32'o15300071342; + endcase + end + + logic [31:0] fhHTYz8JNP73GgkZp; + always_comb begin + case ({wKSnwVGWV, m4Js9aFV4Us, VICULOkZm, XJhsywc8r}) + 4'd6: fhHTYz8JNP73GgkZp = 32'o47241 ^ 32'o62175 ^ 32'd458013848; + 4'ha: fhHTYz8JNP73GgkZp = 32'b00000000000000000111011010010011 ^ 32'b00110011011111001110001010000110; + 4'o7: fhHTYz8JNP73GgkZp = 32'b00000000000000000111100010011110 ^ 32'h7dcc2c86; + 4'o10: fhHTYz8JNP73GgkZp = 32'h229a ^ 32'b00000000000000000111000000001110 ^ 32'h1202b248; + 4'o13: fhHTYz8JNP73GgkZp = 32'b00000000000000000010000010001111 ^ 32'b00000000000000000100000101100110 ^ 32'o13251517010; + 4'b0000: fhHTYz8JNP73GgkZp = 32'o51267 ^ 32'b00000000000000000100000111001100 ^ 32'd110940771; + 4'd1: fhHTYz8JNP73GgkZp = 32'o76263 ^ 32'h3675cebe; + 4'h4: fhHTYz8JNP73GgkZp = 32'o75250 ^ 32'b00011100000101100010111010111001; + 4'b1110: fhHTYz8JNP73GgkZp = 32'd18561 ^ 32'd1483794795; + 4'h9: fhHTYz8JNP73GgkZp = 32'd19606 ^ 32'o32726 ^ 32'd980015896; + 4'o3: fhHTYz8JNP73GgkZp = 32'd20652 ^ 32'b00000000000000000001001100100101 ^ 32'd868638757; + 4'h2: fhHTYz8JNP73GgkZp = 32'o23260 ^ 32'h19035575; + 4'hd: fhHTYz8JNP73GgkZp = 32'd7812 ^ 32'b00000000000000000001001010111111 ^ 32'o16052401775; + 4'b1100: fhHTYz8JNP73GgkZp = 32'b00000000000000000100101010001100 ^ 32'o13236356763; + 4'o5: fhHTYz8JNP73GgkZp = 32'o22245 ^ 32'b00000111001111101010111000101001; + 4'o17: fhHTYz8JNP73GgkZp = 32'b00000000000000000111001001111101 ^ 32'd7759 ^ 32'b00100111001011110111011100110001; + endcase + end + assign m4Js9aFV4Us = UmLX == (32'd22117 ^ 32'd32555 ^ 32'd10590); + + always_ff @(posedge clk_i) begin + if(zZF) begin + parity_en <= '0; + end else if (b5l5UfftZRDTX1AD2[32'h7906 ^ 32'h12c0 ^ 32'h6bc7]) begin + parity_en <= '0; + end + else if(fhHTYz8JNP73GgkZp[32'o1770 ^ 32'o1771]) begin + parity_en <= FFDK4sD9m7; + end + else begin + parity_en <= parity_en; + end + end + + logic P0EEllcI4VCU; + assign P0EEllcI4VCU = UmLX == (32'o62726 ^ 32'd26050); + always_comb begin + case ({m4Js9aFV4Us, P0EEllcI4VCU, VICULOkZm, XJhsywc8r, wKSnwVGWV, fcS5S0IailtPh}) + 6'b010011: WLGbSSV5YzHmlpmqLI = 32'h7a7f ^ 32'o6421703407; + 6'h1a: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000100101001100010 ^ 32'h62321c5f; + 6'h2f: WLGbSSV5YzHmlpmqLI = 32'o63023 ^ 32'h722d90fd; + 6'd28: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000001111001011011 ^ 32'h3d02 ^ 32'd1738296917; + 6'he: WLGbSSV5YzHmlpmqLI = 32'd10385 ^ 32'h1e9099e6; + 6'b000110: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000010111010110001 ^ 32'd100341241; + 6'h7: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000101100010101101 ^ 32'o74006 ^ 32'h4af4ca7f; + 6'd53: WLGbSSV5YzHmlpmqLI = 32'h61fd ^ 32'd21334 ^ 32'b01101010110001001001010101000010; + 6'o61: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000011101000001100 ^ 32'd1070093101; + 6'o76: WLGbSSV5YzHmlpmqLI = 32'h5d9 ^ 32'o4453034147; + 6'd36: WLGbSSV5YzHmlpmqLI = 32'o67076 ^ 32'o65503 ^ 32'o236115274; + 6'h29: WLGbSSV5YzHmlpmqLI = 32'o40054 ^ 32'b00000000000000000100100000101100 ^ 32'd438005057; + 6'b111011: WLGbSSV5YzHmlpmqLI = 32'h7e4 ^ 32'h5a9eb098; + 6'o21: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000010011010000110 ^ 32'o73640 ^ 32'b00101111111101010100111111100010; + 6'd40: WLGbSSV5YzHmlpmqLI = 32'h1630 ^ 32'b01100011100010011101000101001101; + 6'h37: WLGbSSV5YzHmlpmqLI = 32'd13814 ^ 32'd1499541943; + 6'o17: WLGbSSV5YzHmlpmqLI = 32'h528d ^ 32'h6c10 ^ 32'o7462474716; + 6'd34: WLGbSSV5YzHmlpmqLI = 32'd6725 ^ 32'b01111010100000111001101011110101; + 6'd2: WLGbSSV5YzHmlpmqLI = 32'o3277 ^ 32'h1b1d ^ 32'd1165033499; + 6'h30: WLGbSSV5YzHmlpmqLI = 32'h100f ^ 32'b00000000000000000111011001101110 ^ 32'o6552062231; + 6'b010110: WLGbSSV5YzHmlpmqLI = 32'o74164 ^ 32'd1434393388; + 6'b111101: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000101101111011101 ^ 32'b00000000000000000100011101100000 ^ 32'd909162724; + 6'd57: WLGbSSV5YzHmlpmqLI = 32'd2543 ^ 32'b00001000011000100101001011101011; + 6'b101011: WLGbSSV5YzHmlpmqLI = 32'd15905 ^ 32'o14605 ^ 32'd426889412; + 6'o72: WLGbSSV5YzHmlpmqLI = 32'd13291 ^ 32'o13620560216; + 6'b011111: WLGbSSV5YzHmlpmqLI = 32'd7248 ^ 32'h39d2009f; + 6'b101100: WLGbSSV5YzHmlpmqLI = 32'o64036 ^ 32'd2115225742; + 6'o46: WLGbSSV5YzHmlpmqLI = 32'd16951 ^ 32'b00000000000000000111011011010100 ^ 32'b01011100001111100101001100110011; + 6'b100011: WLGbSSV5YzHmlpmqLI = 32'o42102 ^ 32'b00000000000000000010010101111011 ^ 32'b01100001010001000101101011010101; + 6'o30: WLGbSSV5YzHmlpmqLI = 32'o46155 ^ 32'b00001111100010110010101101111001; + 6'h12: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000101000010000010 ^ 32'h3d68 ^ 32'o5006130516; + 6'o52: WLGbSSV5YzHmlpmqLI = 32'h1425 ^ 32'd21437 ^ 32'h6c10c5c1; + 6'o35: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000100100001010111 ^ 32'b00001111100001110110000101101011; + 6'd13: WLGbSSV5YzHmlpmqLI = 32'd32404 ^ 32'o5267624761; + 6'b111000: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000101111111110011 ^ 32'd9391 ^ 32'b00000010001110111100111110000100; + 6'd63: WLGbSSV5YzHmlpmqLI = 32'o27726 ^ 32'd21232 ^ 32'h60c73c71; + 6'b100111: WLGbSSV5YzHmlpmqLI = 32'h6c33 ^ 32'd1348383130; + 6'h33: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000000111000000101 ^ 32'b00000000000000000100011111000110 ^ 32'o1413653112; + 6'b110010: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000110010000001000 ^ 32'b00101000100110011110100011100100; + 6'h8: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000010110010100110 ^ 32'o11036124126; + 6'b100000: WLGbSSV5YzHmlpmqLI = 32'd17996 ^ 32'd55914332; + 6'o3: WLGbSSV5YzHmlpmqLI = 32'o30274 ^ 32'o4415063561; + 6'o11: WLGbSSV5YzHmlpmqLI = 32'h56a3 ^ 32'o44537 ^ 32'o7406347521; + 6'o13: WLGbSSV5YzHmlpmqLI = 32'd10907 ^ 32'd1539340531; + 6'h25: WLGbSSV5YzHmlpmqLI = 32'h183a ^ 32'h321abce3; + 6'b110110: WLGbSSV5YzHmlpmqLI = 32'hbfa ^ 32'b00000000000000000001100100011111 ^ 32'o13474325645; + 6'h17: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000010001001110000 ^ 32'o15121 ^ 32'd1851010648; + 6'b001100: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000101010010011000 ^ 32'h1ab7 ^ 32'o2022343312; + 6'o36: WLGbSSV5YzHmlpmqLI = 32'o71124 ^ 32'o44222 ^ 32'o7444464371; + 6'd46: WLGbSSV5YzHmlpmqLI = 32'o36027 ^ 32'o65335 ^ 32'd371448084; + 6'b010000: WLGbSSV5YzHmlpmqLI = 32'h7c89 ^ 32'd1941236341; + 6'b010100: WLGbSSV5YzHmlpmqLI = 32'h247b ^ 32'o44370 ^ 32'd1196722951; + 6'd27: WLGbSSV5YzHmlpmqLI = 32'd29790 ^ 32'o73472 ^ 32'h5602858c; + 6'b000101: WLGbSSV5YzHmlpmqLI = 32'd1205 ^ 32'h6c76 ^ 32'd1912730239; + 6'b011001: WLGbSSV5YzHmlpmqLI = 32'h2066 ^ 32'h6ba9 ^ 32'd942376155; + 6'o1: WLGbSSV5YzHmlpmqLI = 32'o56303 ^ 32'b00111110001100010100011111001011; + 6'o4: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000101101010111000 ^ 32'h4fc2c804; + 6'h34: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000011100000000001 ^ 32'o13201041555; + 6'd45: WLGbSSV5YzHmlpmqLI = 32'b00000000000000000001001000011010 ^ 32'b00000000000000000010010100010101 ^ 32'hb1fbcbe; + 6'b001010: WLGbSSV5YzHmlpmqLI = 32'd159 ^ 32'd1516813251; + 6'b010101: WLGbSSV5YzHmlpmqLI = 32'o47170 ^ 32'h693d2bc0; + 6'd60: WLGbSSV5YzHmlpmqLI = 32'h31e1 ^ 32'd1326516696; + 6'h21: WLGbSSV5YzHmlpmqLI = 32'd28745 ^ 32'o14753 ^ 32'o102622513; + 6'h0: WLGbSSV5YzHmlpmqLI = 32'd12999 ^ 32'd3981 ^ 32'o16012611657; + endcase + end + + assign wKSnwVGWV = pEo & qICjuvAOmWmr; + assign VICULOkZm = UmLX == (32'h148f ^ 32'o12253); + + logic [31:0] vBjc8EzRDlz48WXa4k; + always_comb begin + case ({m4Js9aFV4Us, P0EEllcI4VCU, VICULOkZm, XJhsywc8r, wKSnwVGWV, fcS5S0IailtPh}) + 6'd9: vBjc8EzRDlz48WXa4k = 32'b00000000000000000001110000100110 ^ 32'd1968865001; + 6'b110111: vBjc8EzRDlz48WXa4k = 32'b00000000000000000111101101111010 ^ 32'b00000000000000000100111000100110 ^ 32'o10303624447; + 6'h38: vBjc8EzRDlz48WXa4k = 32'o47563 ^ 32'd22966 ^ 32'b01011000111000010111000111010011; + 6'b001110: vBjc8EzRDlz48WXa4k = 32'd28180 ^ 32'd1770718541; + 6'd44: vBjc8EzRDlz48WXa4k = 32'o26641 ^ 32'o47214 ^ 32'd1269075633; + 6'b101101: vBjc8EzRDlz48WXa4k = 32'h579e ^ 32'o6642351503; + 6'o76: vBjc8EzRDlz48WXa4k = 32'h4b5d ^ 32'b00000000000000000111110001100111 ^ 32'd2002868800; + 6'o31: vBjc8EzRDlz48WXa4k = 32'd26089 ^ 32'b00000000000000000101101011101001 ^ 32'h25c93bcb; + 6'd30: vBjc8EzRDlz48WXa4k = 32'b00000000000000000011011111010111 ^ 32'h4bcd7ab8; + 6'h3f: vBjc8EzRDlz48WXa4k = 32'h755a ^ 32'h683eb3f6; + 6'd50: vBjc8EzRDlz48WXa4k = 32'o24614 ^ 32'o741700252; + 6'b110001: vBjc8EzRDlz48WXa4k = 32'b00000000000000000111111110001111 ^ 32'b00000000000000000010101101110101 ^ 32'h25a4e761; + 6'b101011: vBjc8EzRDlz48WXa4k = 32'b00000000000000000000001110100101 ^ 32'd2244 ^ 32'h68c578ae; + 6'h5: vBjc8EzRDlz48WXa4k = 32'b00000000000000000111010000110101 ^ 32'h217d ^ 32'd278675848; + 6'o60: vBjc8EzRDlz48WXa4k = 32'o52623 ^ 32'd1522064583; + 6'o17: vBjc8EzRDlz48WXa4k = 32'd6161 ^ 32'o55517 ^ 32'b01001001001111001110001011011010; + 6'o50: vBjc8EzRDlz48WXa4k = 32'd1456 ^ 32'h4076583a; + 6'o24: vBjc8EzRDlz48WXa4k = 32'h69ff ^ 32'd1647636143; + 6'o47: vBjc8EzRDlz48WXa4k = 32'd23475 ^ 32'o13355467573; + 6'o52: vBjc8EzRDlz48WXa4k = 32'h59a9 ^ 32'd269481827; + 6'o71: vBjc8EzRDlz48WXa4k = 32'd31087 ^ 32'h7630562; + 6'h18: vBjc8EzRDlz48WXa4k = 32'o35755 ^ 32'h6a83bd37; + 6'd29: vBjc8EzRDlz48WXa4k = 32'o6733 ^ 32'h4a379444; + 6'd7: vBjc8EzRDlz48WXa4k = 32'h482e ^ 32'o26415 ^ 32'h159216ab; + 6'd28: vBjc8EzRDlz48WXa4k = 32'o61737 ^ 32'o26101 ^ 32'h12fd684a; + 6'o22: vBjc8EzRDlz48WXa4k = 32'o13006 ^ 32'o26247 ^ 32'b01011001100101010111010000011010; + 6'o32: vBjc8EzRDlz48WXa4k = 32'd4070 ^ 32'h20b1 ^ 32'd1493582438; + 6'd8: vBjc8EzRDlz48WXa4k = 32'h722a ^ 32'd29398 ^ 32'd1335986429; + 6'd16: vBjc8EzRDlz48WXa4k = 32'b00000000000000000100001000001101 ^ 32'h2117 ^ 32'o7123071615; + 6'd0: vBjc8EzRDlz48WXa4k = 32'b00000000000000000111100001001010 ^ 32'h7ecc ^ 32'b00111101001001011100000000011001; + 6'd13: vBjc8EzRDlz48WXa4k = 32'h4418 ^ 32'h4fbe ^ 32'o10512704470; + 6'd46: vBjc8EzRDlz48WXa4k = 32'h19a ^ 32'b00000000000000000101101000011100 ^ 32'h50de6cc1; + 6'b100110: vBjc8EzRDlz48WXa4k = 32'd1979 ^ 32'b00101111001000100000011100100000; + 6'b101001: vBjc8EzRDlz48WXa4k = 32'h2fac ^ 32'o76464 ^ 32'd1859925953; + 6'h3: vBjc8EzRDlz48WXa4k = 32'o20074 ^ 32'd1241899107; + 6'o33: vBjc8EzRDlz48WXa4k = 32'o34742 ^ 32'b00001000000101001000010101000110; + 6'hc: vBjc8EzRDlz48WXa4k = 32'b00000000000000000001101000011100 ^ 32'o14507726611; + 6'd2: vBjc8EzRDlz48WXa4k = 32'h4c43 ^ 32'h5dfc9c0f; + 6'd51: vBjc8EzRDlz48WXa4k = 32'o51610 ^ 32'o2712712356; + 6'd61: vBjc8EzRDlz48WXa4k = 32'd8545 ^ 32'o5010064657; + 6'd52: vBjc8EzRDlz48WXa4k = 32'h7d85 ^ 32'b00000000000000000111110011001110 ^ 32'o2373371533; + 6'o23: vBjc8EzRDlz48WXa4k = 32'h4002 ^ 32'h7270 ^ 32'o13661424031; + 6'd47: vBjc8EzRDlz48WXa4k = 32'd11159 ^ 32'o17745 ^ 32'd1507346480; + 6'b001011: vBjc8EzRDlz48WXa4k = 32'b00000000000000000111000000011111 ^ 32'o16126427520; + 6'd34: vBjc8EzRDlz48WXa4k = 32'o57711 ^ 32'o47362 ^ 32'o6556706570; + 6'b010001: vBjc8EzRDlz48WXa4k = 32'd27658 ^ 32'o13440363525; + 6'd53: vBjc8EzRDlz48WXa4k = 32'b00000000000000000010011110000001 ^ 32'd923797700; + 6'h20: vBjc8EzRDlz48WXa4k = 32'b00000000000000000000101111010000 ^ 32'b00001111101110010101110100011011; + 6'o6: vBjc8EzRDlz48WXa4k = 32'o17061 ^ 32'o10271662043; + 6'o4: vBjc8EzRDlz48WXa4k = 32'o45070 ^ 32'b00010101110001010001001000101000; + 6'ha: vBjc8EzRDlz48WXa4k = 32'b00000000000000000100011000100011 ^ 32'o77146 ^ 32'o5725726402; + 6'h17: vBjc8EzRDlz48WXa4k = 32'o10761 ^ 32'o47530 ^ 32'd846604252; + 6'o37: vBjc8EzRDlz48WXa4k = 32'd25044 ^ 32'o76632 ^ 32'o12032654357; + 6'b111010: vBjc8EzRDlz48WXa4k = 32'd9068 ^ 32'd1215680840; + 6'o45: vBjc8EzRDlz48WXa4k = 32'd23998 ^ 32'o20113 ^ 32'o11606433661; + 6'o1: vBjc8EzRDlz48WXa4k = 32'o21107 ^ 32'd17556 ^ 32'o2065074715; + 6'b100100: vBjc8EzRDlz48WXa4k = 32'h33c2 ^ 32'b00000000000000000101101010000011 ^ 32'b00000110011010101111000010000000; + 6'o26: vBjc8EzRDlz48WXa4k = 32'h67f4 ^ 32'o14126711433; + 6'o25: vBjc8EzRDlz48WXa4k = 32'h3df8 ^ 32'b01011010011010110100011011110000; + 6'o43: vBjc8EzRDlz48WXa4k = 32'b00000000000000000000100111000101 ^ 32'h74b56408; + 6'o73: vBjc8EzRDlz48WXa4k = 32'b00000000000000000100110101101000 ^ 32'b00000000000000000010101100001111 ^ 32'b01110110100101111011001000011000; + 6'o66: vBjc8EzRDlz48WXa4k = 32'd20862 ^ 32'd2142 ^ 32'b01011110101000000011101011001001; + 6'd60: vBjc8EzRDlz48WXa4k = 32'd30564 ^ 32'b01100101011101001001000011101011; + 6'b100001: vBjc8EzRDlz48WXa4k = 32'b00000000000000000011010111001101 ^ 32'b00100101111010001111100000001000; + endcase + end + + logic [31:0] jMTaMbqs055c0zWDyuyX; + always_comb begin + case ({VICULOkZm, XJhsywc8r, wKSnwVGWV, pEo, qICjuvAOmWmr}) + 5'ha: jMTaMbqs055c0zWDyuyX = 32'o73053 ^ 32'd2060447563; + 5'd1: jMTaMbqs055c0zWDyuyX = 32'd21071 ^ 32'b00001110111001010101111011000110; + 5'o36: jMTaMbqs055c0zWDyuyX = 32'o63740 ^ 32'h70d4 ^ 32'b01010001001001000110011110010010; + 5'o3: jMTaMbqs055c0zWDyuyX = 32'd9800 ^ 32'o4546566315; + 5'd23: jMTaMbqs055c0zWDyuyX = 32'b00000000000000000001011111111100 ^ 32'h4293 ^ 32'h38506077; + 5'h18: jMTaMbqs055c0zWDyuyX = 32'd16889 ^ 32'b01111111000001000101110000010000; + 5'h1f: jMTaMbqs055c0zWDyuyX = 32'h11dc ^ 32'h6066bf0e; + 5'hc: jMTaMbqs055c0zWDyuyX = 32'b00000000000000000100101000100100 ^ 32'd17145 ^ 32'b01111001101001110100010101100100; + 5'b10110: jMTaMbqs055c0zWDyuyX = 32'd28160 ^ 32'd1424638173; + 5'd17: jMTaMbqs055c0zWDyuyX = 32'd7186 ^ 32'h1fe2 ^ 32'h3f956080; + 5'b11010: jMTaMbqs055c0zWDyuyX = 32'h15f2 ^ 32'd5099 ^ 32'h4913b6d4; + 5'h9: jMTaMbqs055c0zWDyuyX = 32'h4c2f ^ 32'h71a0 ^ 32'b00001100000001010001000000000011; + 5'd29: jMTaMbqs055c0zWDyuyX = 32'h3de3 ^ 32'b00101001010010010101111101110110; + 5'o16: jMTaMbqs055c0zWDyuyX = 32'o17035 ^ 32'h4e89 ^ 32'h7bdf00ac; + 5'd15: jMTaMbqs055c0zWDyuyX = 32'h4819 ^ 32'd5201 ^ 32'b00110000101110111110101010011101; + 5'o4: jMTaMbqs055c0zWDyuyX = 32'd20548 ^ 32'h10344c94; + 5'b11001: jMTaMbqs055c0zWDyuyX = 32'o65765 ^ 32'o47043 ^ 32'b01100100111111110111000011100011; + 5'b00101: jMTaMbqs055c0zWDyuyX = 32'd31297 ^ 32'd5304 ^ 32'h23b36249; + 5'd19: jMTaMbqs055c0zWDyuyX = 32'b00000000000000000111000000001011 ^ 32'o4472612632; + 5'd2: jMTaMbqs055c0zWDyuyX = 32'b00000000000000000111110001001100 ^ 32'd17247 ^ 32'h555c1aef; + 5'd28: jMTaMbqs055c0zWDyuyX = 32'h13e7 ^ 32'b00010111110000011101010111100011; + 5'b10100: jMTaMbqs055c0zWDyuyX = 32'h1a07 ^ 32'h713a ^ 32'h7b647c68; + 5'd27: jMTaMbqs055c0zWDyuyX = 32'd27114 ^ 32'h1f7c ^ 32'b00111111111000011101110000111011; + 5'h6: jMTaMbqs055c0zWDyuyX = 32'h243d ^ 32'd484145837; + 5'd13: jMTaMbqs055c0zWDyuyX = 32'o72040 ^ 32'o6326065451; + 5'h7: jMTaMbqs055c0zWDyuyX = 32'b00000000000000000100111000111010 ^ 32'h2048 ^ 32'b00010100100110011101000001011011; + 5'h15: jMTaMbqs055c0zWDyuyX = 32'b00000000000000000100010000000100 ^ 32'h37ed0d9d; + 5'b10010: jMTaMbqs055c0zWDyuyX = 32'b00000000000000000100011000001110 ^ 32'd26026 ^ 32'd2088858357; + 5'o0: jMTaMbqs055c0zWDyuyX = 32'd10323 ^ 32'd460283331; + 5'hb: jMTaMbqs055c0zWDyuyX = 32'o20050 ^ 32'd438053772; + 5'o10: jMTaMbqs055c0zWDyuyX = 32'o74066 ^ 32'b00000000000000000110011000010000 ^ 32'o1737740073; + 5'b10000: jMTaMbqs055c0zWDyuyX = 32'b00000000000000000111001000010110 ^ 32'd212527463; + endcase + end + + logic [31:0] cI7ozekBmfu12; + always_comb begin + case ({VICULOkZm, XJhsywc8r, wKSnwVGWV, pEo, qICjuvAOmWmr}) + 5'd19: cI7ozekBmfu12 = 32'o57146 ^ 32'h3fc7 ^ 32'd479659813; + 5'h16: cI7ozekBmfu12 = 32'h5c5b ^ 32'd1434596568; + 5'b01111: cI7ozekBmfu12 = 32'b00000000000000000011011001110101 ^ 32'h6ba09ff2; + 5'h11: cI7ozekBmfu12 = 32'd2669 ^ 32'd334215551; + 5'b10101: cI7ozekBmfu12 = 32'h325f ^ 32'o45527 ^ 32'h3356711; + 5'd24: cI7ozekBmfu12 = 32'b00000000000000000011000001010100 ^ 32'o16260 ^ 32'h2f09e87d; + 5'hd: cI7ozekBmfu12 = 32'o61174 ^ 32'o16426 ^ 32'b01001101010000001000101111111010; + 5'b00011: cI7ozekBmfu12 = 32'o12243 ^ 32'h1d7c ^ 32'h5eb2511b; + 5'o32: cI7ozekBmfu12 = 32'h2e49 ^ 32'o67010 ^ 32'o2457411160; + 5'd20: cI7ozekBmfu12 = 32'd2147 ^ 32'o5045051261; + 5'o33: cI7ozekBmfu12 = 32'o54106 ^ 32'd957482061; + 5'b00010: cI7ozekBmfu12 = 32'h6aa7 ^ 32'b00001010000011100001111010011011; + 5'hc: cI7ozekBmfu12 = 32'b00000000000000000011100001111111 ^ 32'b01111100000000111011011100110001; + 5'h0: cI7ozekBmfu12 = 32'd5806 ^ 32'o46044 ^ 32'h28b2451; + 5'o1: cI7ozekBmfu12 = 32'b00000000000000000100000010101010 ^ 32'd4588 ^ 32'd1605026255; + 5'o31: cI7ozekBmfu12 = 32'h44d ^ 32'b00000000000000000010100001000000 ^ 32'b00001000101110101111101011011110; + 5'o6: cI7ozekBmfu12 = 32'd4761 ^ 32'h6ed5 ^ 32'h113e251c; + 5'd8: cI7ozekBmfu12 = 32'b00000000000000000110011010010001 ^ 32'o75145 ^ 32'b01100000100111001100000000111011; + 5'b00100: cI7ozekBmfu12 = 32'h3ea0 ^ 32'h7ece5d64; + 5'b11100: cI7ozekBmfu12 = 32'b00000000000000000000001001000010 ^ 32'b00000000000000000111100110011001 ^ 32'b01111100010101000001010111000100; + 5'o35: cI7ozekBmfu12 = 32'o26077 ^ 32'b01000111101111101110001100110110; + 5'o37: cI7ozekBmfu12 = 32'h37 ^ 32'b00000000000000000100101011110001 ^ 32'b01010111011111111110011000000101; + 5'd9: cI7ozekBmfu12 = 32'o35212 ^ 32'h3d1fddd0; + 5'b01110: cI7ozekBmfu12 = 32'b00000000000000000000110001111000 ^ 32'o12534110346; + 5'b01010: cI7ozekBmfu12 = 32'd25735 ^ 32'o45675 ^ 32'b00000001011000111010011100011111; + 5'b01011: cI7ozekBmfu12 = 32'b00000000000000000000111010000011 ^ 32'd415529667; + 5'b00101: cI7ozekBmfu12 = 32'h689c ^ 32'h30983181; + 5'b10010: cI7ozekBmfu12 = 32'b00000000000000000011010001101010 ^ 32'b00000000000000000111100111111111 ^ 32'h1b000e39; + 5'o20: cI7ozekBmfu12 = 32'd24689 ^ 32'h6e6f ^ 32'd1284891543; + 5'd7: cI7ozekBmfu12 = 32'o36225 ^ 32'b01111000111111111010010000001100; + 5'h17: cI7ozekBmfu12 = 32'h658 ^ 32'd778613074; + 5'o36: cI7ozekBmfu12 = 32'o53073 ^ 32'o15466557266; + endcase + end + + always_ff @(posedge clk_i) begin + if(zZF) begin + X5ldx3X4a <= '0; + end else if (jMTaMbqs055c0zWDyuyX[32'd15091 ^ 32'd28271 ^ 32'o65644 ^ 32'h4036 ^ 32'b00000000000000000110010001100010 ^ 32'o15555]) begin + X5ldx3X4a <= '0; + end + else if(cI7ozekBmfu12[32'o13355 ^ 32'b00000000000000000101111011100001 ^ 32'o44011]) begin + case(UmLX) + 32'h00: X5ldx3X4a <= data; + 32'h04: X5ldx3X4a <= valid; + 32'h08: X5ldx3X4a <= busy; + 32'h0c: X5ldx3X4a <= baudrate; + 32'h10: X5ldx3X4a <= parity_en; + 32'h14: X5ldx3X4a <= stopbit; + default: X5ldx3X4a <= X5ldx3X4a; + endcase + end + else begin + X5ldx3X4a <= X5ldx3X4a; + end + end + + always_ff @(posedge clk_i) begin + if(zZF) begin + stopbit <= '0; + end else if (WLGbSSV5YzHmlpmqLI[32'b00000000000000000000010011110011 ^ 32'b00000000000000000111111100110011 ^ 32'h7bc1]) begin + stopbit <= '0; + end else if(vBjc8EzRDlz48WXa4k[32'h207b ^ 32'o24252 ^ 32'h7639 ^ 32'h764 ^ 32'o20713 ^ 32'd30353 ^ 32'b00000000000000000010001101000100 ^ 32'o6627]) begin + stopbit <= FFDK4sD9m7; + end + else begin + stopbit <= stopbit; + end + end + assign q0MK89N8qKhS8mdymRsz = FFDK4sD9m7[0]; + assign pEo = req_i; endmodule From 1b94a08c802d0fc19709b4501894e2e3c02e4cd4 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 10 Apr 2024 11:27:42 +0300 Subject: [PATCH 30/32] =?UTF-8?q?=D0=9B=D0=A05.=20=D0=94=D0=BE=D0=B1=D0=B0?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=B2=20=D0=BE=D0=BF?= =?UTF-8?q?=D0=B8=D1=81=D0=B0=D0=BD=D0=B8=D0=B5=20=D1=81=D0=B8=D0=B3=D0=BD?= =?UTF-8?q?=D0=B0=D0=BB=D0=BE=D0=B2=20=D0=BE=D0=BF=D0=BA=D0=BE=D0=B4=D0=BE?= =?UTF-8?q?=D0=B2,=20=D0=BD=D0=B0=20=D0=BA=D0=BE=D1=82=D0=BE=D1=80=D1=8B?= =?UTF-8?q?=D1=85=20=D1=82=D0=BE=D1=82=20=D0=BC=D0=BE=D0=B6=D0=B5=D1=82=20?= =?UTF-8?q?=D0=B8=D0=B7=D0=BC=D0=B5=D0=BD=D0=B8=D1=82=D1=8C=D1=81=D1=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/05. Main decoder/README.md | 36 ++++++++++++++++----------------- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/Labs/05. Main decoder/README.md b/Labs/05. Main decoder/README.md index cf73843..4abe0ca 100644 --- a/Labs/05. Main decoder/README.md +++ b/Labs/05. Main decoder/README.md @@ -148,24 +148,24 @@ _Таблица 4. Значения сигнала `mem_size_o` при пере Управляющие сигналы на выходе декодера зависят от трех полей инструкции: `opcode`, `func3` и `func7`. Обратите внимание, что расположение этих полей одинаково для всех типов инструкций. Это сделано для удобства декодирования. При этом для некоторых инструкций поля `func3` и `func7` могут отсутствовать. -|Название сигнала| Пояснение | -|----------------|------------------------------------------------------------------------------------------------| -|fetched_instr_i |Инструкция для декодирования, считанная из памяти инструкций | -|a_sel_o |Управляющий сигнал мультиплексора для выбора первого операнда АЛУ | -|b_sel_o |Управляющий сигнал мультиплексора для выбора второго операнда АЛУ | -|alu_op_o |Операция АЛУ | -|csr_op_o |Операция модуля CSR | -|csr_we_o |Разрешение на запись в CSR | -|mem_req_o |Запрос на доступ к памяти (часть интерфейса памяти) | -|mem_we_o |Сигнал разрешения записи в память, «write enable» (при равенстве нулю происходит чтение) | -|mem_size_o |Управляющий сигнал для выбора размера слова при чтении-записи в память (часть интерфейса памяти)| -|gpr_we_o |Сигнал разрешения записи в регистровый файл | -|wb_sel_o |Управляющий сигнал мультиплексора для выбора данных, записываемых в регистровый файл | -|illegal_instr_o |Сигнал о некорректной инструкции (на схеме не отмечен) | -|branch_o |Сигнал об инструкции условного перехода | -|jal_o |Сигнал об инструкции безусловного перехода jal | -|jalr_o |Сигнал об инструкции безусловного перехода jalr | -|mret_o |Сигнал об инструкции возврата из прерывания/исключения mret | +|Название сигнала| Пояснение | На каких опкодах может принять ненулевое значение (см. таблицу 6)| +|----------------|------------------------------------------------------------------------------------------------|--------------------------------------------------| +|fetched_instr_i |Инструкция для декодирования, считанная из памяти инструкций | — | +|a_sel_o |Управляющий сигнал мультиплексора для выбора первого операнда АЛУ | На всех кроме `MISC_MEM` и `SYSTEM` | +|b_sel_o |Управляющий сигнал мультиплексора для выбора второго операнда АЛУ | На всех кроме `MISC_MEM` и `SYSTEM` | +|alu_op_o |Операция АЛУ | На всех кроме `MISC_MEM` и `SYSTEM` | +|csr_op_o |Операция модуля CSR | Только на `SYSTEM` | +|csr_we_o |Разрешение на запись в CSR | Только на `SYSTEM` | +|mem_req_o |Запрос на доступ к памяти (часть интерфейса памяти) | На `LOAD` и `STORE` | +|mem_we_o |Сигнал разрешения записи в память, «write enable» (при равенстве нулю происходит чтение) | Только на `STORE` | +|mem_size_o |Управляющий сигнал для выбора размера слова при чтении-записи в память (часть интерфейса памяти)| На `LOAD` и `STORE` | +|gpr_we_o |Сигнал разрешения записи в регистровый файл | На всех кроме `MISC_MEM` | +|wb_sel_o |Управляющий сигнал мультиплексора для выбора данных, записываемых в регистровый файл | На всех кроме `MISC_MEM` | +|illegal_instr_o |Сигнал о некорректной инструкции (на схеме не отмечен) | На всех кроме `JAL`, `LUI`, `AUIPC` | +|branch_o |Сигнал об инструкции условного перехода | Только на `BRANCH` | +|jal_o |Сигнал об инструкции безусловного перехода jal | Только на `JAL` | +|jalr_o |Сигнал об инструкции безусловного перехода jalr | Только на `JALR` | +|mret_o |Сигнал об инструкции возврата из прерывания/исключения mret | Только на `SYSTEM` | _Таблица 5. Описание портов основного дешифратора._ From 60c6011fea8069abd2c46148cabde607170572af Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 10 Apr 2024 11:30:25 +0300 Subject: [PATCH 31/32] =?UTF-8?q?=D0=9B=D0=A05.=20=D0=94=D0=BE=D0=B1=D0=B0?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BF=D0=BE=D0=B4=D0=BF?= =?UTF-8?q?=D0=B8=D1=81=D0=B8=20=D0=BA=20=D1=82=D0=B0=D0=B1=D0=BB=D0=B8?= =?UTF-8?q?=D1=86=D0=B5=206?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/05. Main decoder/README.md | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Labs/05. Main decoder/README.md b/Labs/05. Main decoder/README.md index cf73843..bfa4c10 100644 --- a/Labs/05. Main decoder/README.md +++ b/Labs/05. Main decoder/README.md @@ -194,6 +194,8 @@ _Таблица 5. Описание портов основного дешифр |MISC-MEM|00011 |Не производить операцию | `-` | |SYSTEM |11100 |Записать в `rd` значение `csr`. Обновить значение `csr` с помощью `rs1`. (либо `mret`/`ecall`/`ebreak`)|`csr = csr_op(rs1); rd = csr` | +_Таблица 6. Описание кодов операций_ + ## Инструменты В первую очередь язык описания аппаратуры **SystemVerilog** – это язык. С помощью этого языка человек объясняет либо синтезатору какое он хочет получить устройство, либо симулятору – как он хочет это устройство проверить. Синтезатор – это программа, которая создает из логических элементов цифровое устройство по описанию, предоставляемому человеком. Синтезатору внутри **Vivado** нужно объяснить, что ты от него хочешь. Например, чтобы спросить дорогу у испанца, придется делать это на испанском языке, иначе он ничем не сможет помочь. Если ты знаешь испанский, то это можно сделать еще и разными способами. В **SystemVerilog** точно также – одно и то же устройство можно описать разным кодом, но результат синтеза будет одним и тем же. Однако, часто два разных кода одинаковые по смыслу могут синтезироваться в разную аппаратуру, хотя функционально они будут идентичны, но могут отличаться, например, скоростью работы. Или одни и те же специальные языковые конструкции могут применяться для синтезирования разных цифровых элементов. From bd202d6cf7228bca438fc62dc31d63f4b089ddbb Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 10 Apr 2024 11:39:56 +0300 Subject: [PATCH 32/32] =?UTF-8?q?=D0=9B=D0=A05.=20=D0=94=D0=BE=D0=B1=D0=B0?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D1=83=D1=82=D0=BE=D1=87?= =?UTF-8?q?=D0=BD=D0=B5=D0=BD=D0=B8=D1=8F=20=D0=BF=D0=BE=20CSR?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/05. Main decoder/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Labs/05. Main decoder/README.md b/Labs/05. Main decoder/README.md index bfa4c10..aa36f67 100644 --- a/Labs/05. Main decoder/README.md +++ b/Labs/05. Main decoder/README.md @@ -59,7 +59,7 @@ SYSTEM-инструкции используются для доступа к с Для будущей поддержки прерываний, нам потребуется декодировать инструкции обоих классов. -Обращение к регистрам статуса и контроля осуществляется шестью инструкциями стандартного расширения `Zicsr`. Каждая из этих инструкций (если у нее легальные поля) осуществляет запись в CS-регистры и регистровый файл. +Обращение к регистрам статуса и контроля осуществляется шестью инструкциями стандартного расширения `Zicsr`. Каждая из этих инструкций (если у нее легальные поля) осуществляет запись в CS-регистры и регистровый файл (блоки `Control Status Registers` и `Register File` на _рис. 1_ соответственно). Кроме того, для возврата управления основному потоку инструкций, нужна дополнительная `SYSTEM`-инструкция привилегированного набора команд `MRET`.

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- ADD
- SUB
- XOR
- OR
- AND
- SRA
- SRL
- SLL
- LTS
- LTU
- GES
- GEU
- EQ
- NE
- SLTS
- SLTU
- IN
- JUMP
- LI
- ILL
- NOP
 \ No newline at end of file diff --git a/.pic/Labs/board files/nexys_cobra_structure.drawio.svg b/.pic/Labs/board files/nexys_cobra_structure.drawio.svg new file mode 100644 index 0000000..6aae985 --- /dev/null +++ b/.pic/Labs/board files/nexys_cobra_structure.drawio.svg @@ -0,0 +1,4 @@ + + + +
operation
nexys_CYBERcobra
semseg
sw_i
rst_i
decoder
out
PC
operation
instr_mem
read_data_o
add_i
CYBERcobra
out_o

clk_i

16
/
32
/
8
/
[7:0]
16
/
8
/
32
/
[7:0]
[15:0]
out
PC
 \ No newline at end of file diff --git a/Labs/04. Primitive programmable device/board files/README.md b/Labs/04. Primitive programmable device/board files/README.md index 98ffaf8..7618f4f 100644 --- a/Labs/04. Primitive programmable device/board files/README.md +++ b/Labs/04. Primitive programmable device/board files/README.md @@ -1,11 +1,67 @@ # Проверка работы CYBERcobra на ПЛИС -Если вы не понимаете, что лежит в этой папке, или если надо вспомнить, как прошить ПЛИС, можно воспользоваться [`этой инструкцией`](../../../Vivado%20Basics/Program%20nexys%20a7.md) +После того, как вы проверили на моделировании дизайн, вам необходимо проверить его работу на прототипе в ПЛИС. -Файл [`nexys_cybercobra_demo.sv`](nexys_cybercobra_demo.sv), который нужно запускать с [`демонстрационным файлом инструкций`](demo.mem), является демонстрацией возможностей кобры, реализующий лишь декодирование выходных значений в формат для отображения на семисегментных индикаторах, а вся логика работы реализована инструкциями в текстовом файле. +Инструкция по реализации прототипа описана [здесь](../../../Vivado%20Basics/How%20to%20program%20an%20fpga%20board.md). -Сначала выводится приветствие `≡ALOHA≡`, меняя положение восьми правых переключателей, последовательно нажимая на кнопку `BTND` (на рисунке выделена синим цветом), можно включать или выключать `один` из выбранных сегментов. Кнопка `CPU RESET` (на рисунке выделена красным цветом) возвращает все исходное состояние. Попробуйте погасить все слово, а потом снова его зажечь. +На _рис. 1_ представлена схема прототипа в ПЛИС. -Файл [`nexys_cybercobra.sv`](nexys_cybercobra.sv), который нужно запускать с `вашим файлом инструкций`, так же реализует лишь декодирование выходных значений в формат для отображения на семисегментных индикаторах, но кнопка `BTND` задает тактирующий сигнал, следовательно, нажимая на нее, вы можете пошагово переходить по инструкциям, контролируя правильность работы устройства, для удобства можете в тестовом окружении выставить такое же входное значение, как переключатели sw[15:0] на плате. +![../../../.pic/Labs/board%20files/nexys_cobra_structure.drawio.svg](../../../.pic/Labs/board%20files/nexys_cobra_structure.drawio.svg) -![кобра](../../../.pic/Labs/board%20files/nexys_cobra.jpg) +_Рисунок 1. Структурная схема модуля `nexys_CYBERcobra`._ + +Прототип позволяет потактово исполнять программу, прошитую в память инструкций. Также прототип отображает операцию исполняемую в данный момент. + +> [!NOTE] +> Объект модуля `instr_mem` в модуле `CYBERcobra` **должен** называться `imem`. Т.е. строка создания сущности модуля должна выглядеть следующим образом: `instr_mem  imem(...)`. + +## Описание используемой периферии + +- ### Переключатели. + + Значение с переключателей `SW[15:0]` подаются напрямую на порт `sw_i` модуля дизайна. + +- ### Кнопки + + - `BTND` — при нажатии создает тактовый импульс, поступающий на порт тактирования `clk_i` модуля дизайна. + - `CPU_RESET` — соединен со входом `rst_i` модуля дизайна. + +- ### Светодиоды + + Светодиоды `LED[15:0]` отображают младшие 16 бит значения, выставленного в данный момент на порте `out_o` модуля дизайна. + +- ### Семисегментные индикаторы + + Семисегментные индикаторы разбиты на 3 блока (см. _рис. 1_): + + - `out` — отображают младшие 8 бит значения, выставленного в данный момент на порте `out_o` модуля дизайна, в виде шестнадцатеричного числа. + - `PC` — отображают в виде шестнадцатеричного числа младшие 8 бит программного счетчика, который подается на вход `addr_i` модуля памяти инструкций. + - `operation` — отображают [операцию](#операции-отображаемые-прототипом), исполняемую процессором на текущем такте. + +## Операции, отображаемые прототипом + +Соответствие типа инструкции отображаемой операции: + +1. Вычислительные — соответствует опкодам вычислительных операций АЛУ. +1. Инструкция загрузки константы — `LI` (от **l**oad **i**mmediate). +1. Инструкция загрузки из внешних устройств — `IN` (от **in**put). +1. Безусловный переход — `JUMP`. +1. Инструкций условного перехода — соответствует опкодам операций сравнения АЛУ. + +Во время исполнения вычислительных инструкций и инструкций условного перехода могут встретиться нелегальные операции (отображается как `ILL`, от **ill**egal). Операция считается нелегальной в следующих случаях: + +- Если в поле инструкции, отвечающем за операция АЛУ, указана битовая последовательность, не входящая в диапазон допустимых значений. +- Если инструкция является вычислительной, но в поле инструкции, отвечающем за операция АЛУ, указана битовая последовательность, соответствующая операции, вычисляющей флаг. И обратный случай. + +Инструкция `0 0 11 xxxxxxxxxxxxxxxxxxxxxxxxxxxx` отображается как `NOP` (от **n**o **op**eration). + +Соответствие операции ее отображению на семисегментных индикаторах представлено на _рис. 2_: + +!['../../../.pic/Labs/board%20files/nexys_cobra_operations.drawio.svg'](../../../.pic/Labs/board%20files/nexys_cobra_operations.drawio.svg) + +_Рисунок 2. Соответствие операции ее отображению на семисегментных индикаторах._ + + +## Демонстрационная программа + +В качестве демонстрационной программы, предлагается использовать [example.mem](../example.mem). Описание ее работы можно прочитать в разделе [#финальный обзор](../README.md#финальный-обзор). diff --git a/Labs/04. Primitive programmable device/board files/demo.mem b/Labs/04. Primitive programmable device/board files/demo.mem deleted file mode 100644 index c721581..0000000 --- a/Labs/04. Primitive programmable device/board files/demo.mem +++ /dev/null @@ -1,95 +0,0 @@ -00074221 -00000202 -10844001 -00119463 -10046001 -0006000c -0001400d -0000020e -0000002f -10b0400c -10b4400d -10b8400e -10bc400f -00100010 -00018011 -00001412 -00000073 -00000022 -00000043 -00000084 -00000105 -00000206 -00000407 -00000808 -00001009 -00001fea -2004000b -30040000 -30040000 -30040000 -30040000 -30040000 -30040000 -30040000 -30040000 -30040000 -7ea97ec0 -13ad400b -7c2c4520 -7c2c6540 -7c2c8560 -7c2ca580 -7c2cc5a0 -7c2ce5c0 -7c2d05e0 -7c2d2600 -13866014 -7c500200 -13864014 -7c500200 -13862014 -7c500200 -13860014 -7c500200 -1385e014 -7c500200 -1385c014 -7c500200 -1385a014 -7c500200 -13858014 -7c500200 -bc040400 -13066001 -bc0403c0 -13064001 -bc040380 -13062001 -bc040340 -13060001 -bc040300 -1305e001 -bc0402c0 -1305c001 -bc040280 -1305a001 -bc040240 -13058001 -bc040200 -12066001 -bc0401c0 -12064001 -bc040180 -12062001 -bc040140 -12060001 -bc040100 -1205e001 -bc0400c0 -1205c001 -bc040080 -1205a001 -bc040040 -12058001 -bc041760 diff --git a/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc b/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc index 7c1538a..1b7a70b 100644 --- a/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc +++ b/Labs/04. Primitive programmable device/board files/nexys_a7_100t.xdc @@ -4,47 +4,47 @@ ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project # Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100 }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100}]; +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}]; #Switches -set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { SW[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] -set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { SW[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] -set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { SW[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] -set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { SW[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] -set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { SW[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] -set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { SW[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] -set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { SW[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] -set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] -set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { SW[8] }]; #IO_L24N_T3_34 Sch=sw[8] -set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { SW[9] }]; #IO_25_34 Sch=sw[9] -set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { SW[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] -set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { SW[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] -set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { SW[12] }]; #IO_L24P_T3_35 Sch=sw[12] -set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { SW[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] -set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { SW[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] -set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] +set_property -dict { PACKAGE_PIN J15 IOSTANDARD LVCMOS33 } [get_ports { sw_i[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0] +set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { sw_i[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1] +set_property -dict { PACKAGE_PIN M13 IOSTANDARD LVCMOS33 } [get_ports { sw_i[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2] +set_property -dict { PACKAGE_PIN R15 IOSTANDARD LVCMOS33 } [get_ports { sw_i[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3] +set_property -dict { PACKAGE_PIN R17 IOSTANDARD LVCMOS33 } [get_ports { sw_i[4] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4] +set_property -dict { PACKAGE_PIN T18 IOSTANDARD LVCMOS33 } [get_ports { sw_i[5] }]; #IO_L7N_T1_D10_14 Sch=sw[5] +set_property -dict { PACKAGE_PIN U18 IOSTANDARD LVCMOS33 } [get_ports { sw_i[6] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6] +set_property -dict { PACKAGE_PIN R13 IOSTANDARD LVCMOS33 } [get_ports { sw_i[7] }]; #IO_L5N_T0_D07_14 Sch=sw[7] +set_property -dict { PACKAGE_PIN T8 IOSTANDARD LVCMOS18 } [get_ports { sw_i[8] }]; #IO_L24N_T3_34 Sch=sw[8] +set_property -dict { PACKAGE_PIN U8 IOSTANDARD LVCMOS18 } [get_ports { sw_i[9] }]; #IO_25_34 Sch=sw[9] +set_property -dict { PACKAGE_PIN R16 IOSTANDARD LVCMOS33 } [get_ports { sw_i[10] }]; #IO_L15P_T2_DQS_RDWR_B_14 Sch=sw[10] +set_property -dict { PACKAGE_PIN T13 IOSTANDARD LVCMOS33 } [get_ports { sw_i[11] }]; #IO_L23P_T3_A03_D19_14 Sch=sw[11] +set_property -dict { PACKAGE_PIN H6 IOSTANDARD LVCMOS33 } [get_ports { sw_i[12] }]; #IO_L24P_T3_35 Sch=sw[12] +set_property -dict { PACKAGE_PIN U12 IOSTANDARD LVCMOS33 } [get_ports { sw_i[13] }]; #IO_L20P_T3_A08_D24_14 Sch=sw[13] +set_property -dict { PACKAGE_PIN U11 IOSTANDARD LVCMOS33 } [get_ports { sw_i[14] }]; #IO_L19N_T3_A09_D25_VREF_14 Sch=sw[14] +set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { sw_i[15] }]; #IO_L21P_T3_DQS_14 Sch=sw[15] ### LEDs -#set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { LED[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] -#set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { LED[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] -#set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { LED[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] -#set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { LED[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] -#set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { LED[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] -#set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { LED[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] -#set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { LED[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] -#set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { LED[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] -#set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { LED[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] -#set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { LED[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] -#set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { LED[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] -#set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { LED[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] -#set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { LED[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] -#set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { LED[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] -#set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { LED[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] -#set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { LED[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] +set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { led_o[0] }]; #IO_L18P_T2_A24_15 Sch=led[0] +set_property -dict { PACKAGE_PIN K15 IOSTANDARD LVCMOS33 } [get_ports { led_o[1] }]; #IO_L24P_T3_RS1_15 Sch=led[1] +set_property -dict { PACKAGE_PIN J13 IOSTANDARD LVCMOS33 } [get_ports { led_o[2] }]; #IO_L17N_T2_A25_15 Sch=led[2] +set_property -dict { PACKAGE_PIN N14 IOSTANDARD LVCMOS33 } [get_ports { led_o[3] }]; #IO_L8P_T1_D11_14 Sch=led[3] +set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { led_o[4] }]; #IO_L7P_T1_D09_14 Sch=led[4] +set_property -dict { PACKAGE_PIN V17 IOSTANDARD LVCMOS33 } [get_ports { led_o[5] }]; #IO_L18N_T2_A11_D27_14 Sch=led[5] +set_property -dict { PACKAGE_PIN U17 IOSTANDARD LVCMOS33 } [get_ports { led_o[6] }]; #IO_L17P_T2_A14_D30_14 Sch=led[6] +set_property -dict { PACKAGE_PIN U16 IOSTANDARD LVCMOS33 } [get_ports { led_o[7] }]; #IO_L18P_T2_A12_D28_14 Sch=led[7] +set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { led_o[8] }]; #IO_L16N_T2_A15_D31_14 Sch=led[8] +set_property -dict { PACKAGE_PIN T15 IOSTANDARD LVCMOS33 } [get_ports { led_o[9] }]; #IO_L14N_T2_SRCC_14 Sch=led[9] +set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { led_o[10] }]; #IO_L22P_T3_A05_D21_14 Sch=led[10] +set_property -dict { PACKAGE_PIN T16 IOSTANDARD LVCMOS33 } [get_ports { led_o[11] }]; #IO_L15N_T2_DQS_DOUT_CSO_B_14 Sch=led[11] +set_property -dict { PACKAGE_PIN V15 IOSTANDARD LVCMOS33 } [get_ports { led_o[12] }]; #IO_L16P_T2_CSI_B_14 Sch=led[12] +set_property -dict { PACKAGE_PIN V14 IOSTANDARD LVCMOS33 } [get_ports { led_o[13] }]; #IO_L22N_T3_A04_D20_14 Sch=led[13] +set_property -dict { PACKAGE_PIN V12 IOSTANDARD LVCMOS33 } [get_ports { led_o[14] }]; #IO_L20N_T3_A07_D23_14 Sch=led[14] +set_property -dict { PACKAGE_PIN V11 IOSTANDARD LVCMOS33 } [get_ports { led_o[15] }]; #IO_L21N_T3_DQS_A06_D22_14 Sch=led[15] -### RGB LEDs +## RGB LEDs #set_property -dict { PACKAGE_PIN R12 IOSTANDARD LVCMOS33 } [get_ports { LED16_B }]; #IO_L5P_T0_D06_14 Sch=led16_b #set_property -dict { PACKAGE_PIN M16 IOSTANDARD LVCMOS33 } [get_ports { LED16_G }]; #IO_L10P_T1_D14_14 Sch=led16_g #set_property -dict { PACKAGE_PIN N15 IOSTANDARD LVCMOS33 } [get_ports { LED16_R }]; #IO_L11P_T1_SRCC_14 Sch=led16_r @@ -53,30 +53,30 @@ set_property -dict { PACKAGE_PIN V10 IOSTANDARD LVCMOS33 } [get_ports { SW[15] #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r ##7 segment display -set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca -set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb -set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc -set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd -set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce -set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf -set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp -set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] -set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca_o }]; #IO_L24N_T3_A00_D16_14 Sch=ca +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb_o }]; #IO_25_14 Sch=cb +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc_o }]; #IO_25_15 Sch=cc +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd_o }]; #IO_L17P_T2_A26_15 Sch=cd +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce_o }]; #IO_L13P_T2_MRCC_14 Sch=ce +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf_o }]; #IO_L19P_T3_A10_D26_14 Sch=cf +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg_o }]; #IO_L4P_T0_D04_14 Sch=cg +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp_o }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an_o[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an_o[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an_o[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an_o[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an_o[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an_o[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an_o[6] }]; #IO_L23P_T3_35 Sch=an[6] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an_o[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] ##Buttons -set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn +set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { arstn_i }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc #set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu #set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl -#set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd +# set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { btnr_i }]; #IO_L10N_T1_D15_14 Sch=btnr +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd_i }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd ##Pmod Headers @@ -208,4 +208,4 @@ set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND } #set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn \ No newline at end of file +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn diff --git a/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv b/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv index acd1107..7d14ae3 100644 --- a/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv +++ b/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv @@ -2,91 +2,443 @@ * Project Name : Architectures of Processor Systems (APS) lab work * Organization : National Research University of Electronic Technology (MIET) * Department : Institute of Microdevices and Control Systems -* Author(s) : Nikita Bulavin -* Email(s) : nekkit6@edu.miet.ru +* Author(s) : Alexander Kharlamov +* Email(s) : sasha_xarlamov@org.miet.ru See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. * ------------------------------------------------------------------------------ */ -module nexys_CYBERcobra_dz( - input CLK100, - input resetn, - input BTND, - input [15:0] SW, - output CA, CB, CC, CD, CE, CF, CG, - output [7:0] AN +typedef enum { + INSTR_ALU , // branch and computational + INSTR_LI , // const load + INSTR_IN , // periphery load + INSTR_JUMP , + INSTR_NOP // ws == 3 +} Instruction_type; + +typedef enum { + CH_0 = 0, + CH_1, + CH_2, + CH_3, + CH_4, + CH_5, + CH_6, + CH_7, + CH_8, + CH_9, + CH_A, + CH_b, + CH_c, + CH_d, + CH_E, + CH_F, + CH_G, + CH_L, + CH_n, + CH_o, + CH_r, + CH_S, + CH_t, + CH_u, + CH_X, + CH_P, + CH_J, + CH_q, + CH_i, + CH_m, + + CH_SPACE +} Char; + +typedef struct { + logic ca; + logic cb; + logic cc; + logic cd; + logic ce; + logic cf; + logic cg; + logic dp; +} Semseg; + +module nexys_CYBERcobra( + input logic clk_i, + input logic arstn_i, + input logic [15:0] sw_i, + input logic btnd_i, + output logic [15:0] led_o, + output logic ca_o, + output logic cb_o, + output logic cc_o, + output logic cd_o, + output logic ce_o, + output logic cf_o, + output logic cg_o, + output logic dp_o, + output logic [ 7:0] an_o +); + + logic [31:0] cobra_out; + + logic btnd_sync; + sync sync ( + .clk_i , + .data_i (btnd_i ), + .data_o (btnd_sync) + ); + logic btnd_debounce; + debounce debounce ( + .clk_i , + .arstn_i , + .data_i (btnd_sync ), + .data_o (btnd_debounce) + ); + logic bufg_clk; + BUFG dut_bufg( + .I (btnd_debounce), + .O (bufg_clk ) + ); + + CYBERcobra dut ( + .clk_i (bufg_clk ), + .rst_i (!arstn_i ), + .sw_i (sw_i ), + .out_o (cobra_out ) + ); + + logic [31:0] instr_addr; + logic [31:0] instr; + assign instr_addr = dut.imem.addr_i; + assign instr = dut.imem.read_data_o; + + import alu_opcodes_pkg::*; + + Instruction_type instr_type; + logic [ALU_OP_WIDTH-1:0] alu_op; + logic illegal_instr; + nexys_CYBERcobra_decoder nexys_CYBERcobra_decoder ( + .instr_i (instr ), + .instr_type_o (instr_type ), + .alu_op_o (alu_op ), + .illegal_instr_o (illegal_instr) + ); + + Char op_chars[0:3]; + always_comb begin + op_chars = '{4{CH_SPACE}}; + + case (instr_type) + INSTR_ALU: + case (alu_op) + ALU_ADD : op_chars[0:2] = '{CH_A, CH_d, CH_d}; + ALU_SUB : op_chars[0:2] = '{CH_S, CH_u, CH_b}; + ALU_XOR : op_chars[0:2] = '{CH_X, CH_o, CH_r}; + ALU_OR : op_chars[0:1] = '{CH_o, CH_r}; + ALU_AND : op_chars[0:2] = '{CH_A, CH_n, CH_d}; + ALU_SRA : op_chars[0:2] = '{CH_S, CH_r, CH_A}; + ALU_SRL : op_chars[0:2] = '{CH_S, CH_r, CH_L}; + ALU_SLL : op_chars[0:2] = '{CH_S, CH_L, CH_L}; + ALU_LTS : op_chars[0:2] = '{CH_L, CH_t, CH_S}; + ALU_LTU : op_chars[0:2] = '{CH_L, CH_t, CH_u}; + ALU_GES : op_chars[0:2] = '{CH_G, CH_E, CH_S}; + ALU_GEU : op_chars[0:2] = '{CH_G, CH_E, CH_u}; + ALU_EQ : op_chars[0:1] = '{CH_E, CH_q}; + ALU_NE : op_chars[0:1] = '{CH_n, CH_E}; + ALU_SLTS: op_chars = '{CH_S, CH_L, CH_t, CH_S}; + ALU_SLTU: op_chars = '{CH_S, CH_L, CH_t, CH_u}; + + default : ; + endcase + INSTR_LI : op_chars[0:1] = '{CH_L, CH_i}; + INSTR_JUMP: op_chars = '{CH_J, CH_u, CH_m, CH_P}; + INSTR_NOP : op_chars[0:2] = '{CH_n, CH_o, CH_P}; + INSTR_IN : op_chars[0:1] = '{CH_i, CH_n}; + endcase + end + + Char all_chars[0:7]; + assign all_chars[0:3] = { + Char'(led_o[7:4]) , + Char'(led_o[3:0]) , + Char'(instr_addr[7:4]), + Char'(instr_addr[3:0]) + }; + localparam Char ILL_INSTR_MSG[0:3] = '{CH_i, CH_L, CH_L, CH_SPACE}; + assign all_chars[4:7] = illegal_instr ? ILL_INSTR_MSG : op_chars; + + Semseg all_semsegs[0:7]; + for (genvar semseg_num = 0; semseg_num < 8; ++semseg_num) begin : CHAR2SEMSEG_GEN + char2semseg char2semseg ( + .char_i (all_chars [semseg_num]), + .semseg_o (all_semsegs[semseg_num]) ); - - CYBERcobra dut( - .clk_i(btn), - .rst_i(!resetn), - .sw_i(SW[15:0]), - .out_o(out) - ); - -localparam pwm = 1000; -reg [9:0] counter; -reg [3:0] semseg; -reg [7:0] ANreg; -reg CAr, CBr, CCr, CDr, CEr, CFr, CGr; -reg btn; -wire [31:0] out; - -assign AN[7:0] = ANreg[7:0]; -assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr}; + end -always @(posedge CLK100) begin - if (!resetn) begin - counter <= 'b0; - ANreg[7:0] <= 8'b11111111; - {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; - btn <= BTND; + Semseg all_semsegs_dotted[0:7]; + assign all_semsegs_dotted[0] = all_semsegs[0]; + assign all_semsegs_dotted[2:7] = all_semsegs[2:7]; + assign all_semsegs_dotted[1].ca = all_semsegs[1].ca; + assign all_semsegs_dotted[1].cb = all_semsegs[1].cb; + assign all_semsegs_dotted[1].cc = all_semsegs[1].cc; + assign all_semsegs_dotted[1].cd = all_semsegs[1].cd; + assign all_semsegs_dotted[1].ce = all_semsegs[1].ce; + assign all_semsegs_dotted[1].cf = all_semsegs[1].cf; + assign all_semsegs_dotted[1].cg = all_semsegs[1].cg; + assign all_semsegs_dotted[1].dp = 1'b0; + + Semseg current_semseg; + logic [7:0] an; + semseg_one2many semseg_one2many ( + .clk100m_i (clk_i ), + .arstn_i (arstn_i ), + .all_semsegs_i (all_semsegs_dotted), + .current_semseg_o (current_semseg ), + .an_o (an ) + ); + + assign ca_o = current_semseg.ca; + assign cb_o = current_semseg.cb; + assign cc_o = current_semseg.cc; + assign cd_o = current_semseg.cd; + assign ce_o = current_semseg.ce; + assign cf_o = current_semseg.cf; + assign cg_o = current_semseg.cg; + assign dp_o = current_semseg.dp; + + assign an_o = an; + + assign led_o = cobra_out[15:0]; + +endmodule + +module nexys_CYBERcobra_decoder + import alu_opcodes_pkg::*; +( + input logic [31:0] instr_i, + output Instruction_type instr_type_o, + output logic [ALU_OP_WIDTH-1:0] alu_op_o, + output logic illegal_instr_o +); + + logic j; + logic b; + logic [1:0] ws; + + assign j = instr_i[31]; + assign b = instr_i[30]; + assign ws = instr_i[29:28]; + + logic is_branch_instr; + assign is_branch_instr = b; + + always_comb begin + instr_type_o = INSTR_NOP; + + if (j) begin + instr_type_o = INSTR_JUMP; + end else if (b) begin + instr_type_o = INSTR_ALU; + end else begin + case (ws) + 2'd0: instr_type_o = INSTR_LI; + 2'd1: instr_type_o = INSTR_ALU; + 2'd2: instr_type_o = INSTR_IN; + 2'd3: instr_type_o = INSTR_NOP; + endcase end - else begin - btn <= BTND; - if (counter < pwm) counter = counter + 'b1; - else begin - counter = 'b0; - ANreg[1] <= ANreg[0]; - ANreg[2] <= ANreg[1]; - ANreg[3] <= ANreg[2]; - ANreg[4] <= ANreg[3]; - ANreg[5] <= ANreg[4]; - ANreg[6] <= ANreg[5]; - ANreg[7] <= ANreg[6]; - ANreg[0] <= !(ANreg[6:0] == 7'b1111111); - end - case (1'b0) - ANreg[0]: semseg <= out[3 : 0]; - ANreg[1]: semseg <= out[7 : 4]; - ANreg[2]: semseg <= out[11: 8]; - ANreg[3]: semseg <= out[15:12]; - ANreg[4]: semseg <= out[19:16]; - ANreg[5]: semseg <= out[23:20]; - ANreg[6]: semseg <= out[27:24]; - ANreg[7]: semseg <= out[31:28]; - endcase - case (semseg) - 4'h0: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; - 4'h1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001111; - 4'h2: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0010010; - 4'h3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000110; - 4'h4: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001100; - 4'h5: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100; - 4'h6: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100000; - 4'h7: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001111; - 4'h8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000000; - 4'h9: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000100; - 4'hA: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; - 4'hB: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1100000; - 4'hC: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110001; - 4'hD: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000010; - 4'hE: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110000; - 4'hF: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0111000; - default: {CAr,CBr,CCr,CDr, CEr, CFr, CGr} <= 7'b0111111; - endcase - end + end + + assign alu_op_o = instr_i[27:23]; + + import alu_opcodes_pkg::*; + + typedef enum { + ALU_OP_BRANCH, + ALU_OP_COMPUTATIONAL, + ALU_OP_ILLEGAL + } Alu_op_type; + Alu_op_type alu_op_type; + always_comb begin + alu_op_type = ALU_OP_ILLEGAL; + + case (alu_op_o) inside + ALU_LTS, + ALU_LTU, + ALU_GES, + ALU_GEU, + ALU_EQ , + ALU_NE : alu_op_type = ALU_OP_BRANCH; + + ALU_ADD , + ALU_SUB , + ALU_XOR , + ALU_OR , + ALU_AND , + ALU_SRA , + ALU_SRL , + ALU_SLL , + ALU_SLTS, + ALU_SLTU: alu_op_type = ALU_OP_COMPUTATIONAL; + + default : alu_op_type = ALU_OP_ILLEGAL; + endcase + end + + assign illegal_instr_o = (instr_type_o == INSTR_ALU) && ((alu_op_type == ALU_OP_ILLEGAL) || + ((alu_op_type == ALU_OP_BRANCH) ^ is_branch_instr)); +endmodule + +module char2semseg #( + parameter bit HEX_ONLY = 1'b0 +) ( + input Char char_i, + output Semseg semseg_o +); + + localparam bit [6:0] BLANK = '1; + + logic [6:0] semseg; + always_comb begin + case (char_i) + CH_0 : semseg = ~7'h3F; + CH_1 : semseg = ~7'h06; + CH_2 : semseg = ~7'h5B; + CH_3 : semseg = ~7'h4F; + CH_4 : semseg = ~7'h66; + CH_5 : semseg = ~7'h6D; + CH_6 : semseg = ~7'h7D; + CH_7 : semseg = ~7'h07; + CH_8 : semseg = ~7'h7F; + CH_9 : semseg = ~7'h6F; + CH_A : semseg = ~7'h5F; + CH_b : semseg = ~7'h7C; + CH_c : semseg = ~7'h58; + CH_d : semseg = ~7'h5E; + CH_E : semseg = ~7'h79; + CH_F : semseg = ~7'h71; + CH_G : semseg = ~7'h3D; + CH_L : semseg = ~7'h38; + CH_n : semseg = ~7'h54; + CH_o : semseg = ~7'h5C; + CH_r : semseg = ~7'h50; + CH_S : semseg = ~7'h64; + CH_t : semseg = ~7'h78; + CH_u : semseg = ~7'h1C; + CH_X : semseg = ~7'h76; + CH_P : semseg = ~7'h73; + CH_J : semseg = ~7'h1E; + CH_q : semseg = ~7'h67; + CH_i : semseg = ~7'h30; + CH_m : semseg = ~7'h77; + default : semseg = BLANK; + endcase + end + + assign semseg_o.ca = semseg[0]; + assign semseg_o.cb = semseg[1]; + assign semseg_o.cc = semseg[2]; + assign semseg_o.cd = semseg[3]; + assign semseg_o.ce = semseg[4]; + assign semseg_o.cf = semseg[5]; + assign semseg_o.cg = semseg[6]; + assign semseg_o.dp = 1'b1; + +endmodule + +module semseg_one2many #( + parameter int unsigned SEMSEGS_NUM = 8 +) ( + input Semseg all_semsegs_i[0:SEMSEGS_NUM-1], + input logic clk100m_i, + input logic arstn_i, + output Semseg current_semseg_o, + output logic [7:0] an_o +); + logic clk_i; + assign clk_i = clk100m_i; + + localparam int COUNTER_WIDTH = 10; + logic [COUNTER_WIDTH-1:0] counter_next; + logic [COUNTER_WIDTH-1:0] counter_ff; + assign counter_next = counter_ff + COUNTER_WIDTH'('b1); + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) counter_ff <= '0; + else counter_ff <= counter_next; + end + + logic [7:0] an_ff; + logic [7:0] an_next; + logic an_en; + assign an_next = {an_ff[$left(an_ff)-1:0], an_ff[$left(an_ff)]}; + assign an_en = ~|counter_ff; + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) an_ff <= ~8'b1; + else if (an_en) an_ff <= an_next; + end + + Semseg current_semseg; + always_comb begin + unique case (1'b0) + an_ff[0]: current_semseg = all_semsegs_i[7]; + an_ff[1]: current_semseg = all_semsegs_i[6]; + an_ff[2]: current_semseg = all_semsegs_i[5]; + an_ff[3]: current_semseg = all_semsegs_i[4]; + an_ff[4]: current_semseg = all_semsegs_i[3]; + an_ff[5]: current_semseg = all_semsegs_i[2]; + an_ff[6]: current_semseg = all_semsegs_i[1]; + an_ff[7]: current_semseg = all_semsegs_i[0]; + endcase + end + + assign current_semseg_o = current_semseg; + + assign an_o = an_ff; + +endmodule + +module debounce #( + parameter int unsigned MAX_COUNT = 10000 +) ( + input logic clk_i, + input logic arstn_i, + input logic data_i, + output logic data_o +); + + localparam int COUNTER_WIDTH = $clog2(MAX_COUNT); + logic [COUNTER_WIDTH-1:0] counter_next; + logic [COUNTER_WIDTH-1:0] counter_ff; + assign counter_next = (data_o != data_i) ? counter_ff - COUNTER_WIDTH'('b1) : + COUNTER_WIDTH'(MAX_COUNT); + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) counter_ff <= COUNTER_WIDTH'(MAX_COUNT); + else counter_ff <= counter_next; + end + + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) data_o <= '0; + else if (~|counter_ff) data_o <= data_i; end endmodule + +module sync #( + parameter int unsigned SYNC_STAGES = 3 +) ( + input logic clk_i, + input logic data_i, + output logic data_o +); + + logic [SYNC_STAGES-1:0] sync_buffer_ff; + logic [SYNC_STAGES-1:0] sync_buffer_next; + assign sync_buffer_next = {sync_buffer_ff[$left(sync_buffer_ff)-1:0], data_i}; + always_ff @(posedge clk_i) begin + sync_buffer_ff <= sync_buffer_next; + end + + assign data_o = sync_buffer_ff[$left(sync_buffer_ff)]; + +endmodule diff --git a/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv b/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv deleted file mode 100644 index 91c83e3..0000000 --- a/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv +++ /dev/null @@ -1,85 +0,0 @@ -/* ----------------------------------------------------------------------------- -* Project Name : Architectures of Processor Systems (APS) lab work -* Organization : National Research University of Electronic Technology (MIET) -* Department : Institute of Microdevices and Control Systems -* Author(s) : Nikita Bulavin -* Email(s) : nekkit6@edu.miet.ru - -See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. -* ------------------------------------------------------------------------------ -*/ -module nexys_CYBERcobra( - input CLK100, - input resetn, - input BTND, - input [15:0] SW, - output CA, CB, CC, CD, CE, CF, CG, - output [7:0] AN - ); - - CYBERcobra dut( - .clk_i(CLK100), - .rst_i(!resetn), - .sw_i({7'b0,splash,SW[7:0]}), - .out_o(out) - ); - -localparam pwm = 1000; -reg [9:0] counter; -reg [3:0] semseg; -reg [7:0] ANreg; -reg CAr, CBr, CCr, CDr, CEr, CFr, CGr; -reg [3:0] btn; -reg [10:0] btn_reg; -wire splash; -wire [31:0] out; - -assign AN[7:0] = ANreg[7:0]; -assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr}; -assign splash = ((btn == 4'b1111) ^ btn_reg[10]) && (btn == 4'b1111); - -always @(posedge CLK100) begin - if (!resetn) begin - counter <= 'b0; - ANreg[7:0] <= 8'b11111111; - {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; - btn <= 4'b0; - btn_reg <= 0; - end - else begin - btn <= (btn << 1'b1) + BTND; - btn_reg <= (btn_reg << 1'b1) + (btn == 4'b1111); - if (counter < pwm) counter = counter + 'b1; - else begin - counter = 'b0; - ANreg[1] <= ANreg[0]; - ANreg[2] <= ANreg[1]; - ANreg[3] <= ANreg[2]; - ANreg[4] <= ANreg[3]; - ANreg[5] <= ANreg[4]; - ANreg[6] <= ANreg[5]; - ANreg[7] <= ANreg[6]; - ANreg[0] <= !(ANreg[6:0] == 7'b1111111); - end - case (1'b0) - ANreg[0]: semseg <= out[3 : 0]; - ANreg[1]: semseg <= out[7 : 4]; - ANreg[2]: semseg <= out[11: 8]; - ANreg[3]: semseg <= out[15:12]; - ANreg[4]: semseg <= out[19:16]; - ANreg[5]: semseg <= out[23:20]; - ANreg[6]: semseg <= out[27:24]; - ANreg[7]: semseg <= out[31:28]; - endcase - case (semseg) - 4'h1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //L - 4'h3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110110; //? - 4'h8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //O - 4'hA: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //A - 4'hC: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001000; //H - default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; // - endcase - end - end - -endmodule From 1da4c4fd17aecd599d098533f3deb66bc270d08c Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 19 Mar 2024 11:59:03 +0300 Subject: [PATCH 07/32] =?UTF-8?q?=D0=98=D1=81=D0=BF=D1=80=D0=B0=D0=B2?= =?UTF-8?q?=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D1=81=D1=81=D1=8B=D0=BB=D0=BE?= =?UTF-8?q?=D0=BA=20=D0=B2=20=D1=81=D0=BF=D0=B8=D1=81=D0=BA=D0=B5=20=D0=BB?= =?UTF-8?q?=D0=B0=D0=B1?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/README.md | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/Labs/README.md b/Labs/README.md index d7c28ef..a7e7873 100644 --- a/Labs/README.md +++ b/Labs/README.md @@ -22,10 +22,10 @@ - [10. Подсистема прерывания (IC)](#10-подсистема-прерывания-ic) - [11. Интеграция подсистемы прерывания](#11-интеграция-подсистемы-прерывания) - [12. Увеличение количества источников прерываний с помощью дейзи-цепочки](#12-увеличение-количества-источников-прерываний-с-помощью-дейзи-цепочки) - - [12. Периферийные устройства (PU)](#12-периферийные-устройства-pu) - - [13. Программирование на языке высокого уровня](#13-программирование-на-языке-высокого-уровня) - - [14. Программатор](#14-программатор) - - [15. Оценка производительности](#15-оценка-производительности) + - [13. Периферийные устройства (PU)](#13-периферийные-устройства-pu) + - [14. Программирование на языке высокого уровня](#14-программирование-на-языке-высокого-уровня) + - [15. Программатор](#15-программатор) + - [16. Оценка производительности](#16-оценка-производительности) ## Полезное @@ -106,17 +106,17 @@ ## 1. Сумматор. SystemVerilog (Adder) -![../.pic/Labs/l1.png](../.pic/Labs/lab_01_adder.drawio.svg) +![../.pic/Labs/lab_01_adder.drawio.svg](../.pic/Labs/lab_01_adder.drawio.svg) На первой лабораторной работе изучаются базовые конструкции языка описания аппаратуры SystemVerilog, с помощью которого разрабатывается цифровой сумматор из примитивных логических вентилей, который, в последствии, конфигурируется в ПЛИС и его работа проверяется на отладочном стенде. ## 2. Арифметико-логическое устройство (ALU) -![../.pic/Labs/l2.png](../.pic/Labs/lab_02_alu.drawio.svg) +![../.pic/Labs/lab_02_alu.drawio.svg](../.pic/Labs/lab_02_alu.drawio.svg) На второй лабораторной изучаются новые конструкции языка SystemVerilog, на основе которых разрабатывается блок арифметико-логического устройства (АЛУ). АЛУ — это устройство, на входы которого подаются операнды, над которыми нужно выполнить некоторую операцию (сложение, вычитание и тому подобное) и код операции, которую нужно выполнить, а на выходе появляется результат этой операции. Проще говоря АЛУ - это "калькулятор" процессора. ## 3. Регистровый файл и внешняя память (RF) -![../.pic/Labs/l3.png](../.pic/Labs/lab_03_rf.drawio.svg) +![../.pic/Labs/lab_03_rf.drawio.svg](../.pic/Labs/lab_03_rf.drawio.svg) На третьей лабораторной разрабатываются элементы памяти для будущего процессора: память команд, память данных и регистровый файл. В памяти команд будет храниться программа, которую будет выполнять процессор. В памяти данных хранятся данные, которые будут обрабатываться процессором. Регистровый файл — это маленькая память, тоже с данными, которые могут быть поданы непосредственно на АЛУ. Особенность RISC-архитектур в том, что данные перед обработкой необходимо перенести из памяти данных в регистровый файл, только после этого к ним можно применять различные операции. ## 4. Простейшее программируемое устройство (PPD) @@ -126,12 +126,12 @@ ## 5. Основной дешифратор команд (MD) -![../.pic/Labs/l5.png](../.pic/Labs/lab_05_md.drawio.svg) +![../.pic/Labs/lab_05_md.drawio.svg](../.pic/Labs/lab_05_md.drawio.svg) Пятая лабораторная посвящена разработке устройства управления – основному дешифратору команд. Функция основного дешифратора — получать на вход коды выполняемых операций и преобразовывать их в управляющие сигналы для всех блоков процессора (АЛУ, память, регистровый файл, мультиплексоры). Работа требует внимательности в реализации, а ее результат проверяется заранее подготовленными автоматическими тестами. ## 6. Тракт данных (DP) -![../.pic/Labs/l6.png](../.pic/Labs/lab_06_datapath.drawio.svg) +![../.pic/Labs/lab_06_datapath.drawio.svg](../.pic/Labs/lab_06_datapath.drawio.svg) Разработанные блоки объединяются, образуя тракт данных, управляемый основным дешифратором команд. Результатом шестой лабораторной работы является однотактный процессор, с архитектурой RISC-V, поддерживающий стандартный набор целочисленных инструкций RV32I. В качестве проверки на процессоре запускаются программы, заранее написанные на языке ассемблера RISC-V. Сравнивается результат полученный на симуляторе и на разработанном процессоре. ## 7. Внешняя память @@ -142,7 +142,7 @@ ## 8. Блог загрузки и сохранения данных (LSU) -![../.pic/Labs/l7.png](../.pic/Labs/lab_08_lsu.drawio.svg) +![../.pic/Labs/lab_08_lsu.drawio.svg](../.pic/Labs/lab_08_lsu.drawio.svg) Для корректного исполнения инструкций `LB`, `LBU`, `SB`, `LH`, `LHU`, `SH` мало использовать память с побайтовой записью. Необходимо также уметь управлять этой памятью, определенным образом подготавливать данные как для записи в память данный, так и для записи в регистровый файл, а также следить за тем, чтобы за время работы с памятью, программа процессора не начала исполняться дальше. Все эти задачи возлагаются на специальный модуль, который называется **Блок загрузки и сохранения** (**Load and Store Unit**, **LSU**) @@ -150,11 +150,11 @@ Вспомогательная лабораторная работа по интеграции реализованного ранее блока загрузки и сохранения, а также новой памяти данных в модуль `riscv_unit`. -![../.pic/Labs/l8.png](../.pic/Labs/lab_09_lsu_integration.drawio.svg) +![../.pic/Labs/lab_09_lsu_integration.drawio.svg](../.pic/Labs/lab_09_lsu_integration.drawio.svg) ## 10. Подсистема прерывания (IC) -![../.pic/Labs/l8.png](../.pic/Labs/lab_10_irq.drawio.svg) +![../.pic/Labs/lab_10_irq.drawio.svg](../.pic/Labs/lab_10_irq.drawio.svg) Одной из основных функций процессоров является возможность реагировать на внешние события (дернуть мышку, нажать кнопку и т.п.), автоматически запуская, при их возникновении, соответствующие программы. В данной лабораторной создается и подсистема прерывания, к которой относятся контроллер прерываний с циклическим опросом и блок регистров статуса и управления. @@ -162,7 +162,7 @@ Вспомогательная лабораторная работа по интеграции реализованной ранее подсистемы прерывания. -![../.pic/Labs/l9.png](../.pic/Labs/lab_11_irq_integration.drawio.svg) +![../.pic/Labs/lab_11_irq_integration.drawio.svg](../.pic/Labs/lab_11_irq_integration.drawio.svg) ## 12. Увеличение количества источников прерываний с помощью дейзи-цепочки @@ -170,19 +170,19 @@ ![../.pic/Labs/lab_12_daisy_chain/fig_02.drawio.svg](../.pic/Labs/lab_12_daisy_chain/fig_02.drawio.svg) -## 12. Периферийные устройства (PU) +## 13. Периферийные устройства (PU) -![../.pic/Labs/l9.png](../.pic/Labs/lab_13_peripheral_units.drawio.svg) +![../.pic/Labs/lab_13_peripheral_units.drawio.svg](../.pic/Labs/lab_13_peripheral_units.drawio.svg) В данной лабораторной создаются и подключаются к общей шине и подсистеме прерывания контроллеры периферийных устройств: переключатели, светодиоды, клавиатура, семисегментные дисплеи а также контроллер uart. -## 13. Программирование на языке высокого уровня +## 14. Программирование на языке высокого уровня -![../.pic/Labs/l10.png](../.pic/Labs/lab_13_programming.png) +![../.pic/Labs/lab_14_programming.png](../.pic/Labs/lab_14_programming.png) В рамках данной лабораторной настраивается компилятор GCC для RISC-V и для разработанной системы пишется программное обеспечение на языке программирования C++. -## 14. Программатор +## 15. Программатор До этого момента, исполняемая процессором программа попадала в память инструкций через магический вызов `$readmemh`. Однако реальные микроконтроллеры не обладают такими возможностями. Программа из внешнего мира попадает в них посредством так называемого **программатора** — устройства, обеспечивающего запись программы в память микроконтроллера. Программатор записывает данные в постоянное запоминающее устройство (ПЗУ). Для того, чтобы программа попала из ПЗУ в память инструкций, после запуска контроллера сперва начинает исполняться **загрузчик** (**bootloader**) — небольшая программа, вшитая в память микроконтроллера на этапе изготовления, которая отвечает за первичную инициализацию и подготовку микроконтроллера к выполнению основной программы (включая её перенос из ПЗУ в память инструкций). @@ -190,7 +190,7 @@ ![../.pic/Labs/lab_15_programming_device/fig_04.drawio.svg](../.pic/Labs/lab_15_programming_device.drawio.svg) -## 15. Оценка производительности +## 16. Оценка производительности На текущий момент мы создали процессорную систему, которая способна взаимодействовать с внешним миром посредством периферийных устройств ввода-вывода и программатора. Однако сложно понять, какое место данная система занимает в ряду уже существующих вычислительных систем. From 1441334c543b6b0b0249dea2898703f48a513cf6 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 19 Mar 2024 12:55:27 +0300 Subject: [PATCH 08/32] =?UTF-8?q?=D0=9B=D0=A04.=20=D0=9E=D0=B1=D0=BD=D0=BE?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BF=D0=BE=D1=80=D1=8F?= =?UTF-8?q?=D0=B4=D0=BA=D0=B0=20=D0=B2=D1=8B=D0=BF=D0=BE=D0=BB=D0=BD=D0=B5?= =?UTF-8?q?=D0=BD=D0=B8=D1=8F=20=D1=80=D0=B0=D0=B1=D0=BE=D1=82=D1=8B?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/04. Primitive programmable device/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Labs/04. Primitive programmable device/README.md b/Labs/04. Primitive programmable device/README.md index 8b33479..01632e9 100644 --- a/Labs/04. Primitive programmable device/README.md +++ b/Labs/04. Primitive programmable device/README.md @@ -344,7 +344,7 @@ endmodule 1. В `Design Sources` проекта с предыдущих лаб, создайте `SystemVerilog`-файл `cybercobra.sv`. 2. Опишите в нем модуль процессора с таким же именем и портами, как указано в [задании](#задание-по-реализации-процессора) (обратите внимание на регистр имени модуля). 1. В первую очередь, необходимо создать счетчик команд и все вспомогательные провода. При создании, **следите за разрядностью**. - 2. Затем, необходимо создать экземпляры модулей: памяти инструкции, АЛУ, регистрового файла и сумматора. При подключении сигналов сумматора, надо **обязательно** надо подать нулевое значение на входной бит переноса. Выходной бит переноса подключать не обязательно. + 2. Затем, необходимо создать экземпляры модулей: памяти инструкции, АЛУ, регистрового файла и сумматора. При подключении сигналов сумматора, надо **обязательно** надо подать нулевое значение на входной бит переноса. Выходной бит переноса подключать не обязательно. Объекту памяти инструкций нужно дать имя `imem`. 3. После этого, необходимо описать оставшуюся логику: 1. Программного счетчика 2. Сигнала управления мультиплексором, выбирающим слагаемое для программного счетчика From 3d9901eec4cc75acfbe319e6901db15bae82bec1 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Tue, 19 Mar 2024 15:40:52 +0300 Subject: [PATCH 09/32] Update Multiplexors.md --- Basic Verilog structures/Multiplexors.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Basic Verilog structures/Multiplexors.md b/Basic Verilog structures/Multiplexors.md index cc458a0..8e138fd 100644 --- a/Basic Verilog structures/Multiplexors.md +++ b/Basic Verilog structures/Multiplexors.md @@ -93,7 +93,7 @@ logic Y; always_comb begin // 1) Используется always_comb, т.к. мы хотим подключить // выход мультиплексора к проводу if(S) begin // 2) if-else может находиться только внутри блока always. - Y = D1; // 3) Используется оператор неблокирующего присваивания. + Y = D1; // 3) Используется оператор блокирующего присваивания. end else begin Y = D0; end From 378ebed6d5f97bf08db9478a7367b6e0491107c0 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Fri, 23 Feb 2024 10:46:52 +0300 Subject: [PATCH 10/32] =?UTF-8?q?=D0=9B=D0=A01.=20=D0=A1=D1=82=D0=B8=D0=BB?= =?UTF-8?q?=D0=B8=D1=81=D1=82=D0=B8=D1=87=D0=B5=D1=81=D0=BA=D0=B8=D0=B5=20?= =?UTF-8?q?=D0=BF=D1=80=D0=B0=D0=B2=D0=BA=D0=B8?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/01. Adder/README.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Labs/01. Adder/README.md b/Labs/01. Adder/README.md index 37cfe25..0b5f115 100644 --- a/Labs/01. Adder/README.md +++ b/Labs/01. Adder/README.md @@ -162,7 +162,9 @@ _Рисунок 3. Цифровая схема модуля half_adder, сген Для этого необходимо провести моделирование этой схемы. Во время моделирования на вход схемы подаются входные воздействия. Каждое изменение входных сигналов схемы приводит к каскадному изменению состояний внутренних цепей, которые в итоге меняют выходные сигналы. -Подаваемые на схему входные воздействия формируются верификационным окружением. Верификационное окружение (или тестбенч) — это особый несинтезируемый модуль, который не имеет входных или выходных сигналов. Ему не нужны входные сигналы, поскольку он сам является генератором всех своих внутренних сигналов, и ему не нужны выходные сигналы, поскольку этот модуль ничего не вычисляет, только подает входные воздействия на проверяемый модуль. Внутри тестбенча можно использовать конструкции из несинтезируемого подмножества языка SystemVerilog, в частности программный блок `initial`, в котором команды выполняются последовательно, что делает этот блок чем-то отдаленно похожим на проверяющую программу. Поскольку изменение внутренних цепей происходит с некоторой задержкой относительно изменений входных сигналов, при моделировании есть возможность делать паузы между командами. Это делается с помощью специального символа #, за которым указывается количество отсчётов времени симуляции, которое нужно пропустить перед следующей командой. +Подаваемые на схему входные воздействия формируются верификационным окружением. Верификационное окружение (или тестбенч) — это особый несинтезируемый модуль, который не имеет входных или выходных сигналов. Ему не нужны входные сигналы, поскольку он сам является генератором всех своих внутренних сигналов, и ему не нужны выходные сигналы, поскольку этот модуль ничего не вычисляет, только подает входные воздействия на проверяемый модуль. + +Внутри тестбенча можно использовать конструкции из несинтезируемого подмножества языка SystemVerilog, в частности программный блок `initial`, в котором команды выполняются последовательно, что делает этот блок чем-то отдаленно похожим на проверяющую программу. Поскольку изменение внутренних цепей происходит с некоторой задержкой относительно изменений входных сигналов, при моделировании есть возможность делать паузы между командами. Это делается с помощью специального символа #, за которым указывается количество отсчётов времени симуляции, которое нужно пропустить перед следующей командой. Перед тем как писать верификационное окружение, необходимо составить план того, как будет проводиться проверка устройства (составить верификационный план). @@ -263,7 +265,7 @@ _Рисунок 7. Пример использования конструкци **Обратите внимание**, что данный рисунок не является решением вашей задачи, поскольку у вашего сумматора три входа и два выхода, а у сумматора в примере нет бита переноса. -Несмотря на то, что конструкция выглядит как [~~утка, плавает как утка и крякает как утка~~](https://ru.wikipedia.org/wiki/Утиный_тест) цикл и ведет себя как цикл, нужно понимать, что это не цикл в привычном вам понимании этого слова. Это по-прежнему не программа. Вместо этого, вы выделяете общую закономерность по размещению однотипных модулей на схеме и описываете эту закономерность в виде цикла. +Несмотря на то, что конструкция выглядит как [~~утка, плавает как утка и крякает как утка~~](https://ru.wikipedia.org/wiki/Утиный_тест) цикл и ведет себя как цикл, нужно понимать, что **это не цикл в привычном вам понимании этого слова**. Это по-прежнему не программа. Вместо этого, вы выделяете общую закономерность по размещению однотипных модулей на схеме и описываете эту закономерность в виде цикла. Если вы захотите воспользоваться этой конструкцией, вам будет нужно продумать как вы будете: From 1538f6186fae71bd909039585d1b1312368c4513 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 20 Mar 2024 00:58:29 +0300 Subject: [PATCH 11/32] =?UTF-8?q?=D0=9E=D0=B1=D0=BD=D0=BE=D0=B2=D0=BB?= =?UTF-8?q?=D0=B5=D0=BD=D0=B8=D0=B5=20=D1=81=D0=B0=D0=B1=D0=BC=D0=BE=D0=B4?= =?UTF-8?q?=D1=83=D0=BB=D1=8F=20=D0=BF=D1=80=D0=B5=D0=B7=D0=B5=D0=BD=D1=82?= =?UTF-8?q?=D0=B0=D1=86=D0=B8=D0=B9=20=D0=BB=D0=B5=D0=BA=D1=86=D0=B8=D0=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Lectures/Presentations | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Lectures/Presentations b/Lectures/Presentations index bc6016f..480b999 160000 --- a/Lectures/Presentations +++ b/Lectures/Presentations @@ -1 +1 @@ -Subproject commit bc6016f054db3cac6ab840416f6297b0ad50383c +Subproject commit 480b999cf20b7f8dc2454ee0bc70d86acabc143c From 6b51e7c977e06044d881e24ab5fbb96387e01ed5 Mon Sep 17 00:00:00 2001 From: BROsandr <53278658+BROsandr@users.noreply.github.com> Date: Wed, 20 Mar 2024 14:10:25 +0300 Subject: [PATCH 12/32] =?UTF-8?q?=D0=9B=D0=A04.=20=D0=A1=D0=B1=D1=80=D0=BE?= =?UTF-8?q?=D1=81=20nexys=5Fcobra=20=D1=87=D0=B5=D1=80=D0=B5=D0=B7=20?= =?UTF-8?q?=D0=BA=D0=BD=D0=BE=D0=BF=D0=BA=D1=83=20=D1=82=D0=B0=D0=BA=D1=82?= =?UTF-8?q?=D0=B8=D1=80=D0=BE=D0=B2=D0=B0=D0=BD=D0=B8=D1=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../board files/README.md | 2 +- .../board files/nexys_cybercobra.sv | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/Labs/04. Primitive programmable device/board files/README.md b/Labs/04. Primitive programmable device/board files/README.md index 7618f4f..8a6d9c6 100644 --- a/Labs/04. Primitive programmable device/board files/README.md +++ b/Labs/04. Primitive programmable device/board files/README.md @@ -24,7 +24,7 @@ _Рисунок 1. Структурная схема модуля `nexys_CYBERco - ### Кнопки - `BTND` — при нажатии создает тактовый импульс, поступающий на порт тактирования `clk_i` модуля дизайна. - - `CPU_RESET` — соединен со входом `rst_i` модуля дизайна. + - `CPU_RESET` — соединен со входом `rst_i` модуля дизайна. Поскольку в модуле `CYBERcobra` используется синхронный сброс (то есть сигнал сброса учитывается только во время восходящего фронта тактового сигнала), то для сброса модуля `CYBERcobra` и вложенных в него модулей необходимо при зажатой кнопке сброса еще нажать кнопку тактирования. - ### Светодиоды diff --git a/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv b/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv index 7d14ae3..3032b93 100644 --- a/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv +++ b/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv @@ -89,10 +89,10 @@ module nexys_CYBERcobra( ); logic btnd_debounce; debounce debounce ( - .clk_i , - .arstn_i , - .data_i (btnd_sync ), - .data_o (btnd_debounce) + .clk_i , + .arstn_i (1'b1 ), + .data_i (btnd_sync ), + .data_o (btnd_debounce) ); logic bufg_clk; BUFG dut_bufg( From 28cda201700fa64110f7320b1750b267b705299a Mon Sep 17 00:00:00 2001 From: BROsandr <53278658+BROsandr@users.noreply.github.com> Date: Wed, 20 Mar 2024 14:40:05 +0300 Subject: [PATCH 13/32] =?UTF-8?q?=D0=9B=D0=A06.=20=D0=A0=D0=B5=D1=84=D0=B0?= =?UTF-8?q?=D0=BA=D1=82=D0=BE=D1=80=20=D1=82=D0=BE=D0=BF-=D0=BB=D0=B5?= =?UTF-8?q?=D0=B2=D0=B5=D0=BB=20=D0=BC=D0=BE=D0=B4=D1=83=D0=BB=D1=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Feat(06/board):Переписывание sv модуля * Ref(06/board/top.sv):Изм-ие положения модулей * Fix(06/board):Испр-ие синхронного сброса * Feat(pic/06/board/struct):Доб-ие схемы * Ref(06/board/top.sv):Доб-ие обработки всего opcode * Feat(pic/04/board/op):Доб-ие пикчи * Ref(pic/06/board/op):Обн-ие названий * Feat(06/board/md):Обн-ие md * Feat(06/board/md):Доб-ие инфы про инстр с памятью * Ref(06/board/md):Изм-ие формулирвки для PC --- .../nexys_riscv_unit_operations.drawio.svg | 4 + .../nexys_riscv_unit_structure.drawio.svg | 4 + Labs/06. Datapath/board files/README.md | 45 +- .../board files/nexys_a7_100t.xdc | 42 +- .../board files/nexys_riscv_unit.sv | 446 ++++++++++++------ 5 files changed, 384 insertions(+), 157 deletions(-) create mode 100644 .pic/Labs/board files/nexys_riscv_unit_operations.drawio.svg create mode 100644 .pic/Labs/board files/nexys_riscv_unit_structure.drawio.svg diff --git a/.pic/Labs/board files/nexys_riscv_unit_operations.drawio.svg b/.pic/Labs/board files/nexys_riscv_unit_operations.drawio.svg new file mode 100644 index 0000000..b6bd4e0 --- /dev/null +++ b/.pic/Labs/board files/nexys_riscv_unit_operations.drawio.svg @@ -0,0 +1,4 @@ + + + +
- LOAD
- MISC
- OP_IMM
- AUIPC
- STORE
- OP
- LUI
- BRANCH
- JALR
- JAL
- SYSTEM
- ILL
 \ No newline at end of file diff --git a/.pic/Labs/board files/nexys_riscv_unit_structure.drawio.svg b/.pic/Labs/board files/nexys_riscv_unit_structure.drawio.svg new file mode 100644 index 0000000..aeca1a4 --- /dev/null +++ b/.pic/Labs/board files/nexys_riscv_unit_structure.drawio.svg @@ -0,0 +1,4 @@ + + + +
operation
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Datapath/board files/README.md @@ -1,5 +1,46 @@ # Проверка работы riscv_unit на ПЛИС -Если вы не понимаете, что лежит в этой папке, или если надо вспомнить, как прошить ПЛИС, можно воспользоваться [`этой инструкцией`](../../../Vivado%20Basics/Program%20nexys%20a7.md) +После того, как вы проверили на моделировании дизайн, вам необходимо проверить его работу на прототипе в ПЛИС. -Файл [`nexys_riscv_unit.sv`](nexys_riscv_unit.sv), который нужно запускать с [`демонстрационным файлом инструкций`](../program.mem), является демонстрацией работы вашего ядра, каждое нажатие на BTND формирует тактовый импульс, впоследствии пошагово переходя по инструкциям, которые в свою очередь отображаются на семисегментных индикаторах. +Инструкция по реализации прототипа описана [здесь](../../../Vivado%20Basics/How%20to%20program%20an%20fpga%20board.md). + +На _рис. 1_ представлена схема прототипа в ПЛИС. + +![../../../.pic/Labs/board%20files/nexys_riscv_unit_structure.drawio.svg](../../../.pic/Labs/board%20files/nexys_riscv_unit_structure.drawio.svg) + +_Рисунок 1. Структурная схема модуля `nexys_riscv_unit`._ + +Прототип позволяет потактово исполнять программу, прошитую в память инструкций. Также прототип отображает операцию исполняемую в данный момент. + +> [!NOTE] +> Объект модуля `riscv_core` в модуле `riscv_unit` **должен** называться `core`. Т.е. строка создания сущности модуля должна выглядеть следующим образом: `riscv_core core(...)`. + +## Описание используемой периферии + +- ### Кнопки + + - `BTND` — при нажатии создает тактовый импульс, поступающий на порт тактирования `clk_i` модуля дизайна. Стоит помнить то, что инструкции, работающие с внешней памятью, требуют несколько тактов для своего выполнения. + - `CPU_RESET` — соединен со входом `rst_i` модуля дизайна. Поскольку в модуле `riscv_unit` используется синхронный сброс (то есть сигнал сброса учитывается только во время восходящего фронта тактового сигнала), то для сброса модуля `riscv_unit` и вложенных в него модулей необходимо при зажатой кнопке сброса еще нажать кнопку тактирования. + +- ### Семисегментные индикаторы + + Семисегментные индикаторы разбиты на 2 блока (см. _рис. 1_): + + - `PC` — отображают в виде шестнадцатеричного числа младшие 16 бит программного счетчика, которые вычисляются на основе выхода `instr_addr_o` модуля процессорного ядра. + - `operation` — отображают [операцию](#операции-отображаемые-прототипом), исполняемую процессором на текущем такте. + +## Операции, отображаемые прототипом + +Прототип определяет тип операции по младшим 7 битам инструкции. + +Если тип операции является легальным в рамках процессорного устройства, реализуемого на лабораторных работах, то отображается соответствующий опкод. Опкоды описаны в [riscv_pkg.sv](../../05.%20Main%20decoder/riscv_pkg.sv). Если определенный прототипом тип операции является нелегальным, то на семисегментных индикаторах отображается `ILL` (от **ill**egal). + +Соответствие операции ее отображению на семисегментных индикаторах представлено на _рис. 2_: + +!['../../../.pic/Labs/board%20files/nexys_riscv_unit_operations.drawio.svg'](../../../.pic/Labs/board%20files/nexys_riscv_unit_operations.drawio.svg) + +_Рисунок 2. Соответствие операции ее отображению на семисегментных индикаторах._ + +## Демонстрационная программа + +В качестве демонстрационной программы, предлагается использовать [program.mem](../program.mem). Описание ее работы можно прочитать в разделе [#задание](../README.md#задание). diff --git a/Labs/06. Datapath/board files/nexys_a7_100t.xdc b/Labs/06. Datapath/board files/nexys_a7_100t.xdc index c5553ce..dd198ae 100644 --- a/Labs/06. Datapath/board files/nexys_a7_100t.xdc +++ b/Labs/06. Datapath/board files/nexys_a7_100t.xdc @@ -4,8 +4,8 @@ ## - rename the used ports (in each line, after get_ports) according to the top level signal names in the project # Clock signal -set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { CLK100 }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz -create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CLK100}]; +set_property -dict { PACKAGE_PIN E3 IOSTANDARD LVCMOS33 } [get_ports { clk_i }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz +create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}]; #Switches @@ -53,30 +53,30 @@ create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {CL #set_property -dict { PACKAGE_PIN N16 IOSTANDARD LVCMOS33 } [get_ports { LED17_R }]; #IO_L11N_T1_SRCC_14 Sch=led17_r ##7 segment display -set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }]; #IO_L24N_T3_A00_D16_14 Sch=ca -set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb -set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc -set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }]; #IO_L17P_T2_A26_15 Sch=cd -set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }]; #IO_L13P_T2_MRCC_14 Sch=ce -set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }]; #IO_L19P_T3_A10_D26_14 Sch=cf -set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }]; #IO_L4P_T0_D04_14 Sch=cg -#set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }]; #IO_L19N_T3_A21_VREF_15 Sch=dp -set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] -set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] -set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] -set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] -set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] -set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] -set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6] -set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] +set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { ca_o }]; #IO_L24N_T3_A00_D16_14 Sch=ca +set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { cb_o }]; #IO_25_14 Sch=cb +set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { cc_o }]; #IO_25_15 Sch=cc +set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { cd_o }]; #IO_L17P_T2_A26_15 Sch=cd +set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { ce_o }]; #IO_L13P_T2_MRCC_14 Sch=ce +set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { cf_o }]; #IO_L19P_T3_A10_D26_14 Sch=cf +set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { cg_o }]; #IO_L4P_T0_D04_14 Sch=cg +set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { dp_o }]; #IO_L19N_T3_A21_VREF_15 Sch=dp +set_property -dict { PACKAGE_PIN J17 IOSTANDARD LVCMOS33 } [get_ports { an_o[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0] +set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { an_o[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1] +set_property -dict { PACKAGE_PIN T9 IOSTANDARD LVCMOS33 } [get_ports { an_o[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2] +set_property -dict { PACKAGE_PIN J14 IOSTANDARD LVCMOS33 } [get_ports { an_o[3] }]; #IO_L19P_T3_A22_15 Sch=an[3] +set_property -dict { PACKAGE_PIN P14 IOSTANDARD LVCMOS33 } [get_ports { an_o[4] }]; #IO_L8N_T1_D12_14 Sch=an[4] +set_property -dict { PACKAGE_PIN T14 IOSTANDARD LVCMOS33 } [get_ports { an_o[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5] +set_property -dict { PACKAGE_PIN K2 IOSTANDARD LVCMOS33 } [get_ports { an_o[6] }]; #IO_L23P_T3_35 Sch=an[6] +set_property -dict { PACKAGE_PIN U13 IOSTANDARD LVCMOS33 } [get_ports { an_o[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7] ##Buttons -set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { resetn }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn +set_property -dict { PACKAGE_PIN C12 IOSTANDARD LVCMOS33 } [get_ports { arstn_i }]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn #set_property -dict { PACKAGE_PIN N17 IOSTANDARD LVCMOS33 } [get_ports { BTNC }]; #IO_L9P_T1_DQS_14 Sch=btnc #set_property -dict { PACKAGE_PIN M18 IOSTANDARD LVCMOS33 } [get_ports { BTNU }]; #IO_L4N_T0_D05_14 Sch=btnu #set_property -dict { PACKAGE_PIN P17 IOSTANDARD LVCMOS33 } [get_ports { BTNL }]; #IO_L12P_T1_MRCC_14 Sch=btnl #set_property -dict { PACKAGE_PIN M17 IOSTANDARD LVCMOS33 } [get_ports { BTNR }]; #IO_L10N_T1_D15_14 Sch=btnr -set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd +set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { btnd_i }]; #IO_L9N_T1_DQS_D13_14 Sch=btnd ##Pmod Headers @@ -208,4 +208,4 @@ set_property -dict { PACKAGE_PIN P18 IOSTANDARD LVCMOS33 } [get_ports { BTND } #set_property -dict { PACKAGE_PIN K18 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[1] }]; #IO_L1N_T0_D01_DIN_14 Sch=qspi_dq[1] #set_property -dict { PACKAGE_PIN L14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[2] }]; #IO_L2P_T0_D02_14 Sch=qspi_dq[2] #set_property -dict { PACKAGE_PIN M14 IOSTANDARD LVCMOS33 } [get_ports { QSPI_DQ[3] }]; #IO_L2N_T0_D03_14 Sch=qspi_dq[3] -#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn \ No newline at end of file +#set_property -dict { PACKAGE_PIN L13 IOSTANDARD LVCMOS33 } [get_ports { QSPI_CSN }]; #IO_L6P_T0_FCS_B_14 Sch=qspi_csn diff --git a/Labs/06. Datapath/board files/nexys_riscv_unit.sv b/Labs/06. Datapath/board files/nexys_riscv_unit.sv index f5d5cf1..2ca9045 100644 --- a/Labs/06. Datapath/board files/nexys_riscv_unit.sv +++ b/Labs/06. Datapath/board files/nexys_riscv_unit.sv @@ -2,155 +2,333 @@ * Project Name : Architectures of Processor Systems (APS) lab work * Organization : National Research University of Electronic Technology (MIET) * Department : Institute of Microdevices and Control Systems -* Author(s) : Nikita Bulavin -* Email(s) : nekkit6@edu.miet.ru +* Author(s) : Alexander Kharlamov +* Email(s) : sasha_xarlamov@org.miet.ru See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. * ------------------------------------------------------------------------------ */ +typedef enum { + INSTR_ALU , // branch and computational + INSTR_LI , // const load + INSTR_IN , // periphery load + INSTR_JUMP , + INSTR_NOP // ws == 3 +} Instruction_type; + +typedef enum { + CH_0 = 0, + CH_1, + CH_2, + CH_3, + CH_4, + CH_5, + CH_6, + CH_7, + CH_8, + CH_9, + CH_A, + CH_b, + CH_c, + CH_d, + CH_E, + CH_F, + CH_G, + CH_L, + CH_n, + CH_o, + CH_r, + CH_S, + CH_t, + CH_u, + CH_X, + CH_P, + CH_J, + CH_q, + CH_i, + CH_m, + CH_y, + CH_h, + + CH_SPACE +} Char; + +typedef struct { + logic ca; + logic cb; + logic cc; + logic cd; + logic ce; + logic cf; + logic cg; + logic dp; +} Semseg; + module nexys_riscv_unit( - input CLK100, - input resetn, - input BTND, - output CA, CB, CC, CD, CE, CF, CG, - output [7:0] AN - ); + input logic clk_i, + input logic arstn_i, + input logic btnd_i, + output logic ca_o, + output logic cb_o, + output logic cc_o, + output logic cd_o, + output logic ce_o, + output logic cf_o, + output logic cg_o, + output logic dp_o, + output logic [ 7:0] an_o +); - riscv_unit unit( - .clk_i(btn), - .rst_i(!resetn) - ); + logic btnd_sync; + sync sync ( + .clk_i , + .data_i (btnd_i ), + .data_o (btnd_sync) + ); + logic btnd_debounce; + debounce debounce ( + .clk_i , + .arstn_i (1'b1 ), + .data_i (btnd_sync ), + .data_o (btnd_debounce) + ); + logic bufg_clk; + BUFG dut_bufg( + .I (btnd_debounce), + .O (bufg_clk ) + ); - wire [31:0] instr_addr; - wire [31:0] instr; - reg btn; + riscv_unit unit( + .clk_i (bufg_clk), + .rst_i (!arstn_i) + ); + logic [31:0] instr_addr; + logic [31:0] instr; assign instr_addr = unit.core.instr_addr_o; assign instr = unit.core.instr_i; - localparam pwm = 1000; - reg [9:0] counter; - reg [7:0] semseg; - reg [7:0] ANreg; - reg CAr, CBr, CCr, CDr, CEr, CFr, CGr; + import alu_opcodes_pkg::*; - assign AN[7:0] = ANreg[7:0]; - assign {CA, CB, CC, CD, CE, CF, CG} = {CAr, CBr, CCr, CDr, CEr, CFr, CGr}; + logic illegal_instr; + logic [6:0] opcode; + assign opcode = instr[6:0]; - always @(posedge CLK100) begin - if (!resetn) begin - counter <= 'b0; - ANreg[7:0] <= 8'b11111111; - {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; - btn <= BTND; - end - else begin - btn <= BTND; - if (counter < pwm) counter = counter + 'b1; - else begin - counter = 'b0; - ANreg[1] <= ANreg[0]; - ANreg[2] <= ANreg[1]; - ANreg[3] <= ANreg[2]; - ANreg[4] <= ANreg[3]; - ANreg[5] <= ANreg[4]; - ANreg[6] <= ANreg[5]; - ANreg[7] <= ANreg[6]; - ANreg[0] <= !(ANreg[6:0] == 7'b1111111); - end - if(|(~ANreg[5:4])) begin - case (1'b0) - ANreg[4]: semseg <= instr_addr[3:0]; - ANreg[5]: semseg <= instr_addr[7:4]; - endcase - case (semseg) - 4'h0: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; - 4'h1: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001111; - 4'h2: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0010010; - 4'h3: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000110; - 4'h4: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1001100; - 4'h5: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100; - 4'h6: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100000; - 4'h7: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001111; - 4'h8: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000000; - 4'h9: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000100; - 4'hA: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; - 4'hB: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1100000; - 4'hC: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110001; - 4'hD: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000010; - 4'hE: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110000; - 4'hF: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0111000; - default: {CAr,CBr,CCr,CDr, CEr, CFr, CGr} <= 7'b0111111; - endcase - end else begin - case (1'b0) - ANreg[7]: begin - {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0011000; - end - ANreg[6]: begin - {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110001; - end - ANreg[3]: begin - case(instr[6:2]) - 5'b01101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; //LUI - - 5'b00101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //AUIP A - 5'b11011:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; //JAL - - 5'b11001:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000111; //JALR J - 5'b11000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1100000; //brch b - 5'b00000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //LOAd L - 5'b01000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0100100; //STOr S - 5'b00100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //OPIM O - 5'b01100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; //OP - - default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111001; //ILLE I - endcase - end - ANreg[2]: begin - case(instr[6:2]) - 5'b01101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //LUI L - 5'b00101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000001; //AUIP U - 5'b11011:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000111; //JAL J - 5'b11001:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //JALR A - 5'b11000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111010; //brch r - 5'b00000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //LOAd O - 5'b01000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110000; //StOr t - 5'b00100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0011000; //OPIM P - 5'b01100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111111; //OP - - default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //ILLE L - endcase - end - ANreg[1]: begin - case(instr[6:2]) - 5'b01101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000001; //LUI U - 5'b00101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111001; //AUIP I - 5'b11011:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //JAL A - 5'b11001:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //JALR L - 5'b11000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110010; //brch c - 5'b00000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0001000; //LOAd A - 5'b01000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //STOr O - 5'b00100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111001; //OPIM I - 5'b01100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0000001; //OP O - default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //ILLE L - endcase - end - ANreg[0]: begin - case(instr[6:2]) - 5'b01101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111001; //LUI I - 5'b00101:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0011000; //AUIP P - 5'b11011:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1110001; //JAL L - 5'b11001:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111010; //JALr r - 5'b11000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1101000; //brch h - 5'b00000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1000010; //LOAd d - 5'b01000:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b1111010; //STOr r - 5'b00100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0101010; //OPIM M - 5'b01100:{CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0011000; //OP P - default: {CAr, CBr, CCr, CDr, CEr, CFr, CGr} <= 7'b0110000; //ILLE E - endcase - end - endcase - end - end + Char op_chars[0:3]; + import riscv_pkg::*; + always_comb begin + op_chars = '{4{CH_SPACE}}; + case (opcode) + {LOAD_OPCODE , 2'b11}: op_chars = '{CH_L, CH_o, CH_A, CH_d}; + {MISC_MEM_OPCODE, 2'b11}: op_chars = '{CH_m, CH_i, CH_S, CH_c}; + {OP_IMM_OPCODE , 2'b11}: op_chars = '{CH_o, CH_P, CH_i, CH_m}; + {AUIPC_OPCODE , 2'b11}: op_chars = '{CH_A, CH_u, CH_i, CH_P}; + {STORE_OPCODE , 2'b11}: op_chars = '{CH_S, CH_t, CH_o, CH_r}; + {OP_OPCODE , 2'b11}: op_chars[0:1] = '{CH_o, CH_P}; + {LUI_OPCODE , 2'b11}: op_chars[0:2] = '{CH_L, CH_u, CH_i}; + {BRANCH_OPCODE , 2'b11}: op_chars = '{CH_b, CH_r, CH_c, CH_h}; + {JALR_OPCODE , 2'b11}: op_chars = '{CH_J, CH_A, CH_L, CH_r}; + {JAL_OPCODE , 2'b11}: op_chars[0:2] = '{CH_J, CH_A, CH_L}; + {SYSTEM_OPCODE , 2'b11}: op_chars[0:2] = '{CH_S, CH_y, CH_S}; + + default : op_chars[0:2] = '{CH_i, CH_L, CH_L}; + endcase + end + + Char all_chars[0:7]; + assign all_chars[0:3] = { + Char'(instr_addr[15:12]), + Char'(instr_addr[11: 8]), + Char'(instr_addr[ 7: 4]), + Char'(instr_addr[ 3: 0]) + }; + assign all_chars[4:7] = op_chars; + + Char current_char; + logic [7:0] an; + semseg_one2many #( + .DATA_T (Char) + ) semseg_one2many ( + .clk100m_i (clk_i ), + .arstn_i (arstn_i ), + .all_semsegs_i (all_chars ), + .current_semseg_o (current_char), + .an_o (an ) + ); + + Semseg current_semseg; + char2semseg char2semseg ( + .char_i (current_char ), + .semseg_o (current_semseg) + ); + + assign ca_o = current_semseg.ca; + assign cb_o = current_semseg.cb; + assign cc_o = current_semseg.cc; + assign cd_o = current_semseg.cd; + assign ce_o = current_semseg.ce; + assign cf_o = current_semseg.cf; + assign cg_o = current_semseg.cg; + assign dp_o = current_semseg.dp; + + assign an_o = an; + +endmodule + +module char2semseg #( + parameter bit HEX_ONLY = 1'b0 +) ( + input Char char_i, + output Semseg semseg_o +); + + localparam bit [6:0] BLANK = '1; + + logic [6:0] semseg; + always_comb begin + case (char_i) + CH_0 : semseg = ~7'h3F; + CH_1 : semseg = ~7'h06; + CH_2 : semseg = ~7'h5B; + CH_3 : semseg = ~7'h4F; + CH_4 : semseg = ~7'h66; + CH_5 : semseg = ~7'h6D; + CH_6 : semseg = ~7'h7D; + CH_7 : semseg = ~7'h07; + CH_8 : semseg = ~7'h7F; + CH_9 : semseg = ~7'h6F; + CH_A : semseg = ~7'h5F; + CH_b : semseg = ~7'h7C; + CH_c : semseg = ~7'h58; + CH_d : semseg = ~7'h5E; + CH_E : semseg = ~7'h79; + CH_F : semseg = ~7'h71; + CH_G : semseg = ~7'h3D; + CH_L : semseg = ~7'h38; + CH_n : semseg = ~7'h54; + CH_o : semseg = ~7'h5C; + CH_r : semseg = ~7'h50; + CH_S : semseg = ~7'h64; + CH_t : semseg = ~7'h78; + CH_u : semseg = ~7'h1C; + CH_X : semseg = ~7'h76; + CH_P : semseg = ~7'h73; + CH_J : semseg = ~7'h1E; + CH_q : semseg = ~7'h67; + CH_i : semseg = ~7'h30; + CH_m : semseg = ~7'h77; + CH_y : semseg = ~7'h6E; + CH_h : semseg = ~7'h74; + default : semseg = BLANK; + endcase + end + + assign semseg_o.ca = semseg[0]; + assign semseg_o.cb = semseg[1]; + assign semseg_o.cc = semseg[2]; + assign semseg_o.cd = semseg[3]; + assign semseg_o.ce = semseg[4]; + assign semseg_o.cf = semseg[5]; + assign semseg_o.cg = semseg[6]; + assign semseg_o.dp = 1'b1; + +endmodule + +module semseg_one2many #( + parameter int unsigned SEMSEGS_NUM = 8, + parameter type DATA_T +) ( + input DATA_T all_semsegs_i[0:SEMSEGS_NUM-1], + input logic clk100m_i, + input logic arstn_i, + output DATA_T current_semseg_o, + output logic [7:0] an_o +); + logic clk_i; + assign clk_i = clk100m_i; + + localparam int COUNTER_WIDTH = 10; + logic [COUNTER_WIDTH-1:0] counter_next; + logic [COUNTER_WIDTH-1:0] counter_ff; + assign counter_next = counter_ff + COUNTER_WIDTH'('b1); + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) counter_ff <= '0; + else counter_ff <= counter_next; + end + + logic [7:0] an_ff; + logic [7:0] an_next; + logic an_en; + assign an_next = {an_ff[$left(an_ff)-1:0], an_ff[$left(an_ff)]}; + assign an_en = ~|counter_ff; + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) an_ff <= ~8'b1; + else if (an_en) an_ff <= an_next; + end + + DATA_T current_semseg; + always_comb begin + unique case (1'b0) + an_ff[0]: current_semseg = all_semsegs_i[7]; + an_ff[1]: current_semseg = all_semsegs_i[6]; + an_ff[2]: current_semseg = all_semsegs_i[5]; + an_ff[3]: current_semseg = all_semsegs_i[4]; + an_ff[4]: current_semseg = all_semsegs_i[3]; + an_ff[5]: current_semseg = all_semsegs_i[2]; + an_ff[6]: current_semseg = all_semsegs_i[1]; + an_ff[7]: current_semseg = all_semsegs_i[0]; + endcase + end + + assign current_semseg_o = current_semseg; + + assign an_o = an_ff; + +endmodule + +module debounce #( + parameter int unsigned MAX_COUNT = 10000 +) ( + input logic clk_i, + input logic arstn_i, + input logic data_i, + output logic data_o +); + + localparam int COUNTER_WIDTH = $clog2(MAX_COUNT); + logic [COUNTER_WIDTH-1:0] counter_next; + logic [COUNTER_WIDTH-1:0] counter_ff; + assign counter_next = (data_o != data_i) ? counter_ff - COUNTER_WIDTH'('b1) : + COUNTER_WIDTH'(MAX_COUNT); + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) counter_ff <= COUNTER_WIDTH'(MAX_COUNT); + else counter_ff <= counter_next; + end + + always_ff @(posedge clk_i or negedge arstn_i) begin + if (!arstn_i) data_o <= '0; + else if (~|counter_ff) data_o <= data_i; end endmodule + +module sync #( + parameter int unsigned SYNC_STAGES = 3 +) ( + input logic clk_i, + input logic data_i, + output logic data_o +); + + logic [SYNC_STAGES-1:0] sync_buffer_ff; + logic [SYNC_STAGES-1:0] sync_buffer_next; + assign sync_buffer_next = {sync_buffer_ff[$left(sync_buffer_ff)-1:0], data_i}; + always_ff @(posedge clk_i) begin + sync_buffer_ff <= sync_buffer_next; + end + + assign data_o = sync_buffer_ff[$left(sync_buffer_ff)]; + +endmodule From e5cefc1097e4f77c2b4c1d1e98a24c81b4d85855 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Fri, 22 Mar 2024 15:53:12 +0300 Subject: [PATCH 14/32] =?UTF-8?q?=D0=9B=D0=A03.=20=D0=9E=D0=B1=D0=BD=D0=BE?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BF=D0=BE=D1=80=D1=8F?= =?UTF-8?q?=D0=B4=D0=BA=D0=B0=20=D0=B2=D1=8B=D0=BF=D0=BE=D0=BB=D0=BD=D0=B5?= =?UTF-8?q?=D0=BD=D0=B8=D1=8F=20=D0=B7=D0=B0=D0=B4=D0=B0=D0=BD=D0=B8=D1=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Указано, что: - файл program.mem должен добавляться в Design Sources; - порт на чтение памяти инструкций является асинхроннм. --- Labs/03. Register file and memory/README.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Labs/03. Register file and memory/README.md b/Labs/03. Register file and memory/README.md index f61591e..efdf46a 100644 --- a/Labs/03. Register file and memory/README.md +++ b/Labs/03. Register file and memory/README.md @@ -311,9 +311,10 @@ mоdulе rf_r𝚒sсv( 1. В `Design Sources` проекта с предыдущих лаб, создайте `SystemVerilog`-файл `instr_mem.sv`. 2. Опишите в нем модуль памяти инструкций с таким же именем и портами, как указано в задании. 1. Сперва необходимо создать память (массив регистров). Как это сделать, сказано в разделе [описание памяти на языке SystemVerilog](#описание-памяти-на-языке-systemverilog). Разрядность ячеек памяти должна быть 32 бита, количество ячеек — 1024. - 2. Добавить в проект [`файл с содержимым памяти инструкций`](program.mem). Данный файл будет использоваться при вызове системной функции `$readmemh` в описании памяти инструкций. + 2. Добавить в `Design Sources` проекта [`файл с содержимым памяти инструкций`](program.mem). Данный файл будет использоваться при вызове системной функции `$readmemh` в описании памяти инструкций. 3. К созданной памяти необходимо подключить выход модуля `read_data_o`. При подключении должен быть использован вход модуля `addr_i`, значение которого должно быть уменьшено в 4 раза (побайтовая адресация). 4. При реализации выхода `read_data_o` помните, что обращаясь к ячейке памяти, вам необходимо использовать `[11:2]` биты адреса. + 5. Реализуемый порт на чтение памяти инструкций должен быть **асинхронным**. 3. После описания памяти инструкций, её необходимо проверить с помощью тестового окружения. 1. Тестовое окружение находится [`здесь`](tb_instr_mem.sv). 2. Для запуска симуляции воспользуйтесь [`этой инструкцией`](../../Vivado%20Basics/Run%20Simulation.md). From 48f9c8e30cd45ee2dddeb65ef8f250b2f2d5de81 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Fri, 22 Mar 2024 18:16:44 +0300 Subject: [PATCH 15/32] =?UTF-8?q?=D0=9B=D0=A03.=20=D0=9E=D0=B1=D0=BD=D0=BE?= =?UTF-8?q?=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BE=D0=BF=D0=B8=D1=81?= =?UTF-8?q?=D0=B0=D0=BD=D0=B8=D1=8F=20=D0=BC=D0=BE=D0=B4=D1=83=D0=BB=D0=B5?= =?UTF-8?q?=D0=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/03. Register file and memory/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Labs/03. Register file and memory/README.md b/Labs/03. Register file and memory/README.md index efdf46a..fa9886b 100644 --- a/Labs/03. Register file and memory/README.md +++ b/Labs/03. Register file and memory/README.md @@ -218,7 +218,7 @@ endmodule ### 1. Память инструкций -У данной памяти будет два порта: +У данного модуля будет два входных/выходных сигнала: - 32-битный вход адреса - 32-битный выход данных (асинхронное чтение) @@ -240,7 +240,7 @@ mоdulе instr_mеm( ### 2. Память данных -У данной памяти будет 8 портов: +У данного модуля будет шесть входных/выходных сигналов: - вход тактового синхроимпульса - вход запроса на работу с памятью @@ -269,7 +269,7 @@ mоdulе data_mеm( ### 3. Регистровый файл -У данного модуля будет 8 портов: +У данного модуля будет восемь входных/выходных сигналов: - вход тактового синхроимпульса - вход сигнала разрешения записи From 84c0e9052e1440beb5bd5c2f5daa604dfd0311b5 Mon Sep 17 00:00:00 2001 From: BROsandr <53278658+BROsandr@users.noreply.github.com> Date: Tue, 26 Mar 2024 11:53:15 +0300 Subject: [PATCH 16/32] =?UTF-8?q?=D0=9B=D0=A013.=20=D0=94=D0=BE=D0=B1?= =?UTF-8?q?=D0=B0=D0=B2=D0=BB=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BE=D0=B1=D1=84?= =?UTF-8?q?=D1=83=D1=81=D1=86=D0=B8=D1=80=D0=BE=D0=B2=D0=B0=D0=BD=D0=BD?= =?UTF-8?q?=D0=BE=D0=B3=D0=BE=20=D0=BC=D0=BE=D0=B4=D1=83=D0=BB=D1=8F(#76)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit * Feat(13/uart):Доб-ие обфускации * Feat(13/led):Доб-ие обфускации * Feat(13/led):Распил в lut cntr * Ref(13/led):Улучшение распила в lut cntr * Ref(13/led):Улуч-ие распила led_mode * Feat(13/led):обфускация led_val * Feat(13/led):Обфускация read_data * Fix(13/led):Испр-ие размера read_data_next * Ref(13/led):Уд-ие сигнала soft_reset * Ref(13/led):Уд-ие зависимости по входным сигналам * Ref(13/led):Перестановка строк * Feat(13/led):Разматывание 32'd1 в series * Feat(13/led):Доб-ие xor * Ref(13/led):Уд-ие комментов * Feat(13/led):Доб-ие обфускации имен * Feat(13/led):Деобфускация led_val, led_mode * Fix(13/led):Испр-ие xor * Ref(13/uart_tx):Уд-ие netlist --- Labs/Made-up modules/lab_13.led_sb_ctrl.sv | 450 +++++++++++++++++++++ 1 file changed, 450 insertions(+) create mode 100644 Labs/Made-up modules/lab_13.led_sb_ctrl.sv diff --git a/Labs/Made-up modules/lab_13.led_sb_ctrl.sv b/Labs/Made-up modules/lab_13.led_sb_ctrl.sv new file mode 100644 index 0000000..55a4b8c --- /dev/null +++ b/Labs/Made-up modules/lab_13.led_sb_ctrl.sv @@ -0,0 +1,450 @@ +module led_sb_ctrl( +/* + Часть интерфейса модуля, отвечающая за подключение к системной шине +*/ + input logic clk_i, + input logic rst_i, + input logic req_i, + input logic write_enable_i, + input logic [31:0] addr_i, + input logic [31:0] write_data_i, + output logic [31:0] read_data_o, + +/* + Часть интерфейса модуля, отвечающая за подключение к периферии +*/ + output logic [15:0] led_o +); +logic [15:0] led_val; +logic led_mode; + +logic [31:0] G0jy; + +logic szgbhtISZO6lWdZ0zBq; + +logic GHJMElpRUEQEEP7EcBqK9y7Np; +assign GHJMElpRUEQEEP7EcBqK9y7Np = write_data_i == 1'b1; + +assign led_o = G0jy < 32'd10_000_000 ? led_val : 32'd0; + +logic h9z1ckclZaHUmRYYk; +logic E8on91LjAMIk; +assign h9z1ckclZaHUmRYYk = addr_i == (32'h146 ^ 32'd322); + +localparam bit [31:0] tamX10PbxPLym4NQXMpBFA1ZPCMfu = 32'o6236621706 + 32'h643c9869 + 32'o14614644163 + 32'o16454156121 + 32'h19495cff + 32'h2ae8944a + 32'h625558ec + 32'o4343417451 + 32'o10672076315 + 32'o7506654272 + 32'o12037553653 + 32'h2eb141f2 + 32'h41b71efb + 32'h79e2a9e3 + 32'o16521360506 + 32'o12127600174 + 32'o13364061302 + 32'h12200854 + 32'o11554223770 + 32'h833a88de; + +logic d2Vdz1otfNKET9pkgF4b2ur; +assign E8on91LjAMIk = write_enable_i; +assign d2Vdz1otfNKET9pkgF4b2ur = write_data_i <= tamX10PbxPLym4NQXMpBFA1ZPCMfu; + +logic X9e; +assign X9e = req_i; +logic YaRCbt0zk9bDlW; + +logic kd21aSJpdPn; +always_comb begin + case ({szgbhtISZO6lWdZ0zBq, d2Vdz1otfNKET9pkgF4b2ur, h9z1ckclZaHUmRYYk, E8on91LjAMIk, X9e, GHJMElpRUEQEEP7EcBqK9y7Np}) + 6'b000000: kd21aSJpdPn = 1'b0; + 6'b000001: kd21aSJpdPn = 1'b0; + 6'b000010: kd21aSJpdPn = 1'b0; + 6'b000011: kd21aSJpdPn = 1'b0; + 6'b000100: kd21aSJpdPn = 1'b0; + 6'b000101: kd21aSJpdPn = 1'b0; + 6'b000110: kd21aSJpdPn = 1'b0; + 6'b000111: kd21aSJpdPn = 1'b0; + 6'b001000: kd21aSJpdPn = 1'b0; + 6'b001001: kd21aSJpdPn = 1'b0; + 6'b001010: kd21aSJpdPn = 1'b0; + 6'b001011: kd21aSJpdPn = 1'b0; + 6'b001100: kd21aSJpdPn = 1'b0; + 6'b001101: kd21aSJpdPn = 1'b0; + 6'b001110: kd21aSJpdPn = 1'b0; + 6'b001111: kd21aSJpdPn = 1'b0; + 6'b010000: kd21aSJpdPn = 1'b0; + 6'b010001: kd21aSJpdPn = 1'b0; + 6'b010010: kd21aSJpdPn = 1'b0; + 6'b010011: kd21aSJpdPn = 1'b0; + 6'b010100: kd21aSJpdPn = 1'b0; + 6'b010101: kd21aSJpdPn = 1'b0; + 6'b010110: kd21aSJpdPn = 1'b0; + 6'b010111: kd21aSJpdPn = 1'b0; + 6'b011000: kd21aSJpdPn = 1'b0; + 6'b011001: kd21aSJpdPn = 1'b0; + 6'b011010: kd21aSJpdPn = 1'b0; + 6'b011011: kd21aSJpdPn = 1'b0; + 6'b011100: kd21aSJpdPn = 1'b0; + 6'b011101: kd21aSJpdPn = 1'b0; + 6'b011110: kd21aSJpdPn = 1'b1; + 6'b011111: kd21aSJpdPn = 1'b1; + 6'b100000: kd21aSJpdPn = 1'b0; + 6'b100001: kd21aSJpdPn = 1'b0; + 6'b100010: kd21aSJpdPn = 1'b0; + 6'b100011: kd21aSJpdPn = 1'b0; + 6'b100100: kd21aSJpdPn = 1'b0; + 6'b100101: kd21aSJpdPn = 1'b0; + 6'b100110: kd21aSJpdPn = 1'b0; + 6'b100111: kd21aSJpdPn = 1'b1; + 6'b101000: kd21aSJpdPn = 1'b0; + 6'b101001: kd21aSJpdPn = 1'b0; + 6'b101010: kd21aSJpdPn = 1'b0; + 6'b101011: kd21aSJpdPn = 1'b0; + 6'b101100: kd21aSJpdPn = 1'b0; + 6'b101101: kd21aSJpdPn = 1'b0; + 6'b101110: kd21aSJpdPn = 1'b0; + 6'b101111: kd21aSJpdPn = 1'b1; + 6'b110000: kd21aSJpdPn = 1'b0; + 6'b110001: kd21aSJpdPn = 1'b0; + 6'b110010: kd21aSJpdPn = 1'b0; + 6'b110011: kd21aSJpdPn = 1'b0; + 6'b110100: kd21aSJpdPn = 1'b0; + 6'b110101: kd21aSJpdPn = 1'b0; + 6'b110110: kd21aSJpdPn = 1'b0; + 6'b110111: kd21aSJpdPn = 1'b1; + 6'b111000: kd21aSJpdPn = 1'b0; + 6'b111001: kd21aSJpdPn = 1'b0; + 6'b111010: kd21aSJpdPn = 1'b0; + 6'b111011: kd21aSJpdPn = 1'b0; + 6'b111100: kd21aSJpdPn = 1'b0; + 6'b111101: kd21aSJpdPn = 1'b0; + 6'b111110: kd21aSJpdPn = 1'b1; + 6'b111111: kd21aSJpdPn = 1'b1; + endcase +end + +logic JUTUkxXfzZHi0; +always_comb begin + case ({X9e, YaRCbt0zk9bDlW, E8on91LjAMIk, szgbhtISZO6lWdZ0zBq, GHJMElpRUEQEEP7EcBqK9y7Np}) + 5'b00000: JUTUkxXfzZHi0 = 1'b0; + 5'b00001: JUTUkxXfzZHi0 = 1'b0; + 5'b00010: JUTUkxXfzZHi0 = 1'b0; + 5'b00011: JUTUkxXfzZHi0 = 1'b0; + 5'b00100: JUTUkxXfzZHi0 = 1'b0; + 5'b00101: JUTUkxXfzZHi0 = 1'b0; + 5'b00110: JUTUkxXfzZHi0 = 1'b0; + 5'b00111: JUTUkxXfzZHi0 = 1'b0; + 5'b01000: JUTUkxXfzZHi0 = 1'b1; + 5'b01001: JUTUkxXfzZHi0 = 1'b1; + 5'b01010: JUTUkxXfzZHi0 = 1'b1; + 5'b01011: JUTUkxXfzZHi0 = 1'b1; + 5'b01100: JUTUkxXfzZHi0 = 1'b1; + 5'b01101: JUTUkxXfzZHi0 = 1'b1; + 5'b01110: JUTUkxXfzZHi0 = 1'b1; + 5'b01111: JUTUkxXfzZHi0 = 1'b1; + 5'b10000: JUTUkxXfzZHi0 = 1'b0; + 5'b10001: JUTUkxXfzZHi0 = 1'b0; + 5'b10010: JUTUkxXfzZHi0 = 1'b0; + 5'b10011: JUTUkxXfzZHi0 = 1'b0; + 5'b10100: JUTUkxXfzZHi0 = 1'b0; + 5'b10101: JUTUkxXfzZHi0 = 1'b0; + 5'b10110: JUTUkxXfzZHi0 = 1'b0; + 5'b10111: JUTUkxXfzZHi0 = 1'b0; + 5'b11000: JUTUkxXfzZHi0 = 1'b1; + 5'b11001: JUTUkxXfzZHi0 = 1'b1; + 5'b11010: JUTUkxXfzZHi0 = 1'b1; + 5'b11011: JUTUkxXfzZHi0 = 1'b1; + 5'b11100: JUTUkxXfzZHi0 = 1'b1; + 5'b11101: JUTUkxXfzZHi0 = 1'b1; + 5'b11110: JUTUkxXfzZHi0 = 1'b1; + 5'b11111: JUTUkxXfzZHi0 = 1'b0; + endcase +end + +always_ff @(posedge clk_i) begin + if(rst_i) begin + led_mode <= 1'b0; + end else if(kd21aSJpdPn) begin + led_mode <= JUTUkxXfzZHi0; + end +end +assign YaRCbt0zk9bDlW = write_data_i[0]; + +logic aNirtmfc; +assign aNirtmfc = G0jy < 32'd20_000_000; + +logic [31:0] mTwefHrES; +always_comb begin + case ({aNirtmfc, X9e, E8on91LjAMIk, szgbhtISZO6lWdZ0zBq, led_mode, GHJMElpRUEQEEP7EcBqK9y7Np}) + 6'b000000: mTwefHrES = '0; + 6'b000001: mTwefHrES = '0; + 6'b000010: mTwefHrES = '0; + 6'b000011: mTwefHrES = '0; + 6'b000100: mTwefHrES = '0; + 6'b000101: mTwefHrES = '0; + 6'b000110: mTwefHrES = '0; + 6'b000111: mTwefHrES = '0; + 6'b001000: mTwefHrES = '0; + 6'b001001: mTwefHrES = '0; + 6'b001010: mTwefHrES = '0; + 6'b001011: mTwefHrES = '0; + 6'b001100: mTwefHrES = '0; + 6'b001101: mTwefHrES = '0; + 6'b001110: mTwefHrES = '0; + 6'b001111: mTwefHrES = '0; + 6'b010000: mTwefHrES = '0; + 6'b010001: mTwefHrES = '0; + 6'b010010: mTwefHrES = '0; + 6'b010011: mTwefHrES = '0; + 6'b010100: mTwefHrES = '0; + 6'b010101: mTwefHrES = '0; + 6'b010110: mTwefHrES = '0; + 6'b010111: mTwefHrES = '0; + 6'b011000: mTwefHrES = '0; + 6'b011001: mTwefHrES = '0; + 6'b011010: mTwefHrES = '0; + 6'b011011: mTwefHrES = '0; + 6'b011100: mTwefHrES = '0; + 6'b011101: mTwefHrES = '0; + 6'b011110: mTwefHrES = '0; + 6'b011111: mTwefHrES = '0; + + 6'b100000: mTwefHrES = '0; + 6'b100001: mTwefHrES = '0; + 6'b100010: mTwefHrES = G0jy + 32'b1; + 6'b100011: mTwefHrES = G0jy + 32'b1; + 6'b100100: mTwefHrES = '0; + 6'b100101: mTwefHrES = '0; + 6'b100110: mTwefHrES = G0jy + 32'b1; + 6'b100111: mTwefHrES = G0jy + 32'b1; + 6'b101000: mTwefHrES = '0; + 6'b101001: mTwefHrES = '0; + 6'b101010: mTwefHrES = '0; + 6'b101011: mTwefHrES = '0; + 6'b101100: mTwefHrES = '0; + 6'b101101: mTwefHrES = '0; + 6'b101110: mTwefHrES = G0jy + 32'b1; + 6'b101111: mTwefHrES = G0jy + 32'b1; + 6'b110000: mTwefHrES = '0; + 6'b110001: mTwefHrES = '0; + 6'b110010: mTwefHrES = G0jy + 32'b1; + 6'b110011: mTwefHrES = G0jy + 32'b1; + 6'b110100: mTwefHrES = '0; + 6'b110101: mTwefHrES = '0; + 6'b110110: mTwefHrES = G0jy + 32'b1; + 6'b110111: mTwefHrES = G0jy + 32'b1; + 6'b111000: mTwefHrES = '0; + 6'b111001: mTwefHrES = '0; + 6'b111010: mTwefHrES = G0jy + 32'b1; + 6'b111011: mTwefHrES = G0jy + 32'b1; + 6'b111100: mTwefHrES = '0; + 6'b111101: mTwefHrES = '0; + 6'b111110: mTwefHrES = G0jy + 32'b1; + 6'b111111: mTwefHrES = '0; + endcase +end + +always_ff @(posedge clk_i) begin + if(rst_i) begin + G0jy <= 32'd0; + end else begin + G0jy <= mTwefHrES; + end +end + +logic u8n925jRHw6yY2OA; +assign u8n925jRHw6yY2OA = addr_i == 32'd0; +logic Sksa8hJRDqKf6y; +assign Sksa8hJRDqKf6y = write_data_i[31:16] == 16'd0; + +logic kq8KzeiLOE; +always_comb begin + case ({X9e, E8on91LjAMIk, szgbhtISZO6lWdZ0zBq, GHJMElpRUEQEEP7EcBqK9y7Np, u8n925jRHw6yY2OA, Sksa8hJRDqKf6y}) + 6'b000000: kq8KzeiLOE = 1'b0; + 6'b000001: kq8KzeiLOE = 1'b0; + 6'b000010: kq8KzeiLOE = 1'b0; + 6'b000011: kq8KzeiLOE = 1'b1; + 6'b000100: kq8KzeiLOE = 1'b0; + 6'b000101: kq8KzeiLOE = 1'b0; + 6'b000110: kq8KzeiLOE = 1'b0; + 6'b000111: kq8KzeiLOE = 1'b1; + 6'b001000: kq8KzeiLOE = 1'b0; + 6'b001001: kq8KzeiLOE = 1'b0; + 6'b001010: kq8KzeiLOE = 1'b0; + 6'b001011: kq8KzeiLOE = 1'b1; + 6'b001100: kq8KzeiLOE = 1'b0; + 6'b001101: kq8KzeiLOE = 1'b0; + 6'b001110: kq8KzeiLOE = 1'b0; + 6'b001111: kq8KzeiLOE = 1'b1; + 6'b010000: kq8KzeiLOE = 1'b0; + 6'b010001: kq8KzeiLOE = 1'b0; + 6'b010010: kq8KzeiLOE = 1'b0; + 6'b010011: kq8KzeiLOE = 1'b1; + 6'b010100: kq8KzeiLOE = 1'b0; + 6'b010101: kq8KzeiLOE = 1'b0; + 6'b010110: kq8KzeiLOE = 1'b0; + 6'b010111: kq8KzeiLOE = 1'b1; + 6'b011000: kq8KzeiLOE = 1'b0; + 6'b011001: kq8KzeiLOE = 1'b0; + 6'b011010: kq8KzeiLOE = 1'b0; + 6'b011011: kq8KzeiLOE = 1'b1; + 6'b011100: kq8KzeiLOE = 1'b0; + 6'b011101: kq8KzeiLOE = 1'b0; + 6'b011110: kq8KzeiLOE = 1'b0; + 6'b011111: kq8KzeiLOE = 1'b1; + 6'b100000: kq8KzeiLOE = 1'b0; + 6'b100001: kq8KzeiLOE = 1'b0; + 6'b100010: kq8KzeiLOE = 1'b0; + 6'b100011: kq8KzeiLOE = 1'b1; + 6'b100100: kq8KzeiLOE = 1'b0; + 6'b100101: kq8KzeiLOE = 1'b0; + 6'b100110: kq8KzeiLOE = 1'b0; + 6'b100111: kq8KzeiLOE = 1'b1; + 6'b101000: kq8KzeiLOE = 1'b0; + 6'b101001: kq8KzeiLOE = 1'b0; + 6'b101010: kq8KzeiLOE = 1'b0; + 6'b101011: kq8KzeiLOE = 1'b1; + 6'b101100: kq8KzeiLOE = 1'b0; + 6'b101101: kq8KzeiLOE = 1'b0; + 6'b101110: kq8KzeiLOE = 1'b0; + 6'b101111: kq8KzeiLOE = 1'b1; + 6'b110000: kq8KzeiLOE = 1'b0; + 6'b110001: kq8KzeiLOE = 1'b0; + 6'b110010: kq8KzeiLOE = 1'b0; + 6'b110011: kq8KzeiLOE = 1'b1; + 6'b110100: kq8KzeiLOE = 1'b0; + 6'b110101: kq8KzeiLOE = 1'b0; + 6'b110110: kq8KzeiLOE = 1'b0; + 6'b110111: kq8KzeiLOE = 1'b1; + 6'b111000: kq8KzeiLOE = 1'b0; + 6'b111001: kq8KzeiLOE = 1'b0; + 6'b111010: kq8KzeiLOE = 1'b0; + 6'b111011: kq8KzeiLOE = 1'b1; + 6'b111100: kq8KzeiLOE = 1'b1; + 6'b111101: kq8KzeiLOE = 1'b1; + 6'b111110: kq8KzeiLOE = 1'b1; + 6'b111111: kq8KzeiLOE = 1'b1; + endcase +end + +always_ff @(posedge clk_i) begin + if(rst_i) begin + led_val <= 16'd0; + end + else if(kq8KzeiLOE) begin + led_val <= write_data_i[15:0] & {16{~(X9e & E8on91LjAMIk & szgbhtISZO6lWdZ0zBq & YaRCbt0zk9bDlW & GHJMElpRUEQEEP7EcBqK9y7Np)}}; + end +end + +logic tECGZrHGXNZHv7hEFV; +assign tECGZrHGXNZHv7hEFV = ~|{addr_i[31:3], addr_i[1:0]}; +logic YBnE7pVdlTe8g7B8Mh; +assign YBnE7pVdlTe8g7B8Mh = addr_i[2]; + +logic Sw0wQLq1pYY7; +always_comb begin + case ({YBnE7pVdlTe8g7B8Mh, X9e, szgbhtISZO6lWdZ0zBq, E8on91LjAMIk, tECGZrHGXNZHv7hEFV, GHJMElpRUEQEEP7EcBqK9y7Np}) + 6'b000000: Sw0wQLq1pYY7 = 1'b0; + 6'b000001: Sw0wQLq1pYY7 = 1'b0; + 6'b000010: Sw0wQLq1pYY7 = 1'b0; + 6'b000011: Sw0wQLq1pYY7 = 1'b0; + 6'b000100: Sw0wQLq1pYY7 = 1'b0; + 6'b000101: Sw0wQLq1pYY7 = 1'b0; + 6'b000110: Sw0wQLq1pYY7 = 1'b0; + 6'b000111: Sw0wQLq1pYY7 = 1'b0; + 6'b001000: Sw0wQLq1pYY7 = 1'b0; + 6'b001001: Sw0wQLq1pYY7 = 1'b0; + 6'b001010: Sw0wQLq1pYY7 = 1'b0; + 6'b001011: Sw0wQLq1pYY7 = 1'b0; + 6'b001100: Sw0wQLq1pYY7 = 1'b0; + 6'b001101: Sw0wQLq1pYY7 = 1'b0; + 6'b001110: Sw0wQLq1pYY7 = 1'b0; + 6'b001111: Sw0wQLq1pYY7 = 1'b0; + 6'b010000: Sw0wQLq1pYY7 = 1'b0; + 6'b010001: Sw0wQLq1pYY7 = 1'b0; + 6'b010010: Sw0wQLq1pYY7 = 1'b1; + 6'b010011: Sw0wQLq1pYY7 = 1'b1; + 6'b010100: Sw0wQLq1pYY7 = 1'b0; + 6'b010101: Sw0wQLq1pYY7 = 1'b0; + 6'b010110: Sw0wQLq1pYY7 = 1'b0; + 6'b010111: Sw0wQLq1pYY7 = 1'b0; + 6'b011000: Sw0wQLq1pYY7 = 1'b0; + 6'b011001: Sw0wQLq1pYY7 = 1'b0; + 6'b011010: Sw0wQLq1pYY7 = 1'b1; + 6'b011011: Sw0wQLq1pYY7 = 1'b1; + 6'b011100: Sw0wQLq1pYY7 = 1'b0; + 6'b011101: Sw0wQLq1pYY7 = 1'b1; + 6'b011110: Sw0wQLq1pYY7 = 1'b0; + 6'b011111: Sw0wQLq1pYY7 = 1'b1; + 6'b100000: Sw0wQLq1pYY7 = 1'b0; + 6'b100001: Sw0wQLq1pYY7 = 1'b0; + 6'b100010: Sw0wQLq1pYY7 = 1'b0; + 6'b100011: Sw0wQLq1pYY7 = 1'b0; + 6'b100100: Sw0wQLq1pYY7 = 1'b0; + 6'b100101: Sw0wQLq1pYY7 = 1'b0; + 6'b100110: Sw0wQLq1pYY7 = 1'b0; + 6'b100111: Sw0wQLq1pYY7 = 1'b0; + 6'b101000: Sw0wQLq1pYY7 = 1'b0; + 6'b101001: Sw0wQLq1pYY7 = 1'b0; + 6'b101010: Sw0wQLq1pYY7 = 1'b0; + 6'b101011: Sw0wQLq1pYY7 = 1'b0; + 6'b101100: Sw0wQLq1pYY7 = 1'b0; + 6'b101101: Sw0wQLq1pYY7 = 1'b0; + 6'b101110: Sw0wQLq1pYY7 = 1'b0; + 6'b101111: Sw0wQLq1pYY7 = 1'b0; + 6'b110000: Sw0wQLq1pYY7 = 1'b0; + 6'b110001: Sw0wQLq1pYY7 = 1'b0; + 6'b110010: Sw0wQLq1pYY7 = 1'b1; + 6'b110011: Sw0wQLq1pYY7 = 1'b1; + 6'b110100: Sw0wQLq1pYY7 = 1'b0; + 6'b110101: Sw0wQLq1pYY7 = 1'b0; + 6'b110110: Sw0wQLq1pYY7 = 1'b0; + 6'b110111: Sw0wQLq1pYY7 = 1'b0; + 6'b111000: Sw0wQLq1pYY7 = 1'b0; + 6'b111001: Sw0wQLq1pYY7 = 1'b0; + 6'b111010: Sw0wQLq1pYY7 = 1'b1; + 6'b111011: Sw0wQLq1pYY7 = 1'b1; + 6'b111100: Sw0wQLq1pYY7 = 1'b0; + 6'b111101: Sw0wQLq1pYY7 = 1'b1; + 6'b111110: Sw0wQLq1pYY7 = 1'b0; + 6'b111111: Sw0wQLq1pYY7 = 1'b1; + endcase +end + +logic [31:0] ZuHZYJEOvjcYVi; +always_comb begin + case ({X9e, YBnE7pVdlTe8g7B8Mh, szgbhtISZO6lWdZ0zBq, E8on91LjAMIk, GHJMElpRUEQEEP7EcBqK9y7Np}) + 5'b00000: ZuHZYJEOvjcYVi = read_data_o; + 5'b00001: ZuHZYJEOvjcYVi = read_data_o; + 5'b00010: ZuHZYJEOvjcYVi = read_data_o; + 5'b00011: ZuHZYJEOvjcYVi = read_data_o; + 5'b00100: ZuHZYJEOvjcYVi = read_data_o; + 5'b00101: ZuHZYJEOvjcYVi = read_data_o; + 5'b00110: ZuHZYJEOvjcYVi = read_data_o; + 5'b00111: ZuHZYJEOvjcYVi = read_data_o; + 5'b01000: ZuHZYJEOvjcYVi = read_data_o; + 5'b01001: ZuHZYJEOvjcYVi = read_data_o; + 5'b01010: ZuHZYJEOvjcYVi = read_data_o; + 5'b01011: ZuHZYJEOvjcYVi = read_data_o; + 5'b01100: ZuHZYJEOvjcYVi = read_data_o; + 5'b01101: ZuHZYJEOvjcYVi = read_data_o; + 5'b01110: ZuHZYJEOvjcYVi = read_data_o; + 5'b01111: ZuHZYJEOvjcYVi = read_data_o; + 5'b10000: ZuHZYJEOvjcYVi = {16'd0,led_val}; + 5'b10001: ZuHZYJEOvjcYVi = {16'd0,led_val}; + 5'b10010: ZuHZYJEOvjcYVi = read_data_o; + 5'b10011: ZuHZYJEOvjcYVi = read_data_o; + 5'b10100: ZuHZYJEOvjcYVi = {16'd0,led_val}; + 5'b10101: ZuHZYJEOvjcYVi = {16'd0,led_val}; + 5'b10110: ZuHZYJEOvjcYVi = read_data_o; + 5'b10111: ZuHZYJEOvjcYVi = '0; + 5'b11000: ZuHZYJEOvjcYVi = {31'd0,led_mode}; + 5'b11001: ZuHZYJEOvjcYVi = {31'd0,led_mode}; + 5'b11010: ZuHZYJEOvjcYVi = read_data_o; + 5'b11011: ZuHZYJEOvjcYVi = read_data_o; + 5'b11100: ZuHZYJEOvjcYVi = {31'd0,led_mode}; + 5'b11101: ZuHZYJEOvjcYVi = {31'd0,led_mode}; + 5'b11110: ZuHZYJEOvjcYVi = read_data_o; + 5'b11111: ZuHZYJEOvjcYVi = '0; + endcase +end + +always_ff @(posedge clk_i) begin + if(rst_i) begin + read_data_o <= 32'd0; + end + else if(Sw0wQLq1pYY7) begin + read_data_o <= ZuHZYJEOvjcYVi; + end +end + +assign szgbhtISZO6lWdZ0zBq = addr_i == 32'h24; +endmodule From e13794228c0d1ec740648e70a2413d7481573037 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Sun, 31 Mar 2024 21:15:13 +0300 Subject: [PATCH 17/32] =?UTF-8?q?=D0=9B=D0=A05.=20=D0=A3=D0=B4=D0=B0=D0=BB?= =?UTF-8?q?=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BA=D0=BE=D0=BC=D0=BC=D0=B5=D0=BD?= =?UTF-8?q?=D1=82=D0=B0=D1=80=D0=B8=D1=8F=20=D0=B8=D0=B7=20=D0=BF=D1=80?= =?UTF-8?q?=D0=BE=D1=82=D0=BE=D1=82=D0=B8=D0=BF=D0=B0=20=D0=BC=D0=BE=D0=B4?= =?UTF-8?q?=D1=83=D0=BB=D1=8F?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- Labs/05. Main decoder/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Labs/05. Main decoder/README.md b/Labs/05. Main decoder/README.md index 300baaf..5344b75 100644 --- a/Labs/05. Main decoder/README.md +++ b/Labs/05. Main decoder/README.md @@ -258,7 +258,7 @@ module decoder_riscv ( output logic mem_we_o, output logic [2:0] mem_size_o, output logic gpr_we_o, - output logic [1:0] wb_sel_o, //write back selector + output logic [1:0] wb_sel_o, output logic illegal_instr_o, output logic branch_o, output logic jal_o, From b059a316b62752457dddf60d187c0c6163a2641f Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Sun, 31 Mar 2024 23:36:25 +0300 Subject: [PATCH 18/32] =?UTF-8?q?=D0=9B=D0=A05.=20=D0=94=D0=BE=D0=BF=D0=BE?= =?UTF-8?q?=D0=BB=D0=BD=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BA=D0=BE=D0=B4=D0=B8?= =?UTF-8?q?=D1=80=D0=BE=D0=B2=D0=B0=D0=BD=D0=B8=D1=8F=20SYSTEM=20=D0=B8?= =?UTF-8?q?=D0=BD=D1=81=D1=82=D1=80=D1=83=D0=BA=D1=86=D0=B8=D0=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Добавлено пояснение касательно хардкода инструкций ecall, ebreak, mret. --- .pic/Labs/lab_05_decoder/rv32i_summary.png | Bin 245654 -> 244577 bytes .pic/Labs/lab_05_decoder/rv32i_summary.xlsx | Bin 17617 -> 17642 bytes Labs/05. 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