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Update lab_03.tb_register_file.sv

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Andrei Solodovnikov
2024-09-11 23:18:52 +03:00
committed by GitHub
parent 3bd2559291
commit 773568589f
1 changed files with 0 additions and 2 deletions
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Labs/03. Register file and memory/lab_03.tb_register_file.sv
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@@ -168,8 +168,6 @@ module lab_03_tb_register_file();
RA1 <= 5'd2; RA1 <= 5'd2;
RA2 <= 5'd2; RA2 <= 5'd2;
@(posedge CLK); @(posedge CLK);
RD1ref = 2;
RD2ref = 2;
if(RD1ref !== RD1) begin if(RD1ref !== RD1) begin
$display("time = %0t, address %h, RD1. Invalid data %h, correct data %h", $time, RA1, RD1, RD1ref); $display("time = %0t, address %h, RD1. Invalid data %h, correct data %h", $time, RA1, RD1, RD1ref);
err_count = err_count + 1; err_count = err_count + 1;