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ЛР16. Рефактор методички (#97)

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* ЛР16. Рефактор методички

* Apply suggestions from code review
This commit is contained in:
Andrei Solodovnikov
2024-07-29 16:15:48 +03:00
committed by GitHub
parent 59510a522b
commit 73e521687e
4 changed files with 115 additions and 106 deletions
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4
Labs/16. Coremark/Makefile
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@@ -26,7 +26,6 @@ OBJS = $(src) startup.o core_list_join.o core_matrix.o core_portme.o core_state.
LINK_SCRIPT = linker_script.ld
OUTPUT = coremark
OUTPUT_PROD = $(addprefix $(OUTPUT), .mem _instr.mem _data.mem .elf _disasm.S)
# OUTPUT_PROD :=$(OUTPUT_PROD) $(addprefix tb_$(OUTPUT), .mem _instr.mem _data.mem .elf _disasm.S)
INC_DIRS = "./"
SRC_DIR = ./src
@@ -44,9 +43,6 @@ harvard: $(OUTPUT).elf $(OUTPUT)_disasm.S size
# $< означает "первая зависимость"
${OBJCOPY} -O verilog --verilog-data-width=4 -j .data -j .sdata -j .bss $< $(OUTPUT)_data.mem
${OBJCOPY} -O verilog --verilog-data-width=4 -j .text $< $(OUTPUT)_instr.mem
${OBJCOPY} -O verilog -j .data -j .sdata -j .bss $< tb_$(OUTPUT)_data.mem
${OBJCOPY} -O verilog -j .text $< tb_$(OUTPUT)_instr.mem
sed -i '1d' $(OUTPUT)_data.mem
princeton: $(OUTPUT).elf $(OUTPUT)_disasm.S size
${OBJCOPY} -O verilog --verilog-data-width=4 --remove-section=.comment $< $(OUTPUT).mem