From 71cb2f3099a1be75746b3403b9a285556907503b Mon Sep 17 00:00:00 2001
From: Andrei Solodovnikov <VoultBoy@yandex.ru>
Date: Tue, 19 May 2026 13:41:13 +0300
Subject: [PATCH] =?UTF-8?q?=D0=98=D1=81=D0=BF=D1=80=D0=B0=D0=B2=D0=BB?=
 =?UTF-8?q?=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=B8=D0=BC=D0=B5=D0=BD=D0=B8=20?=
 =?UTF-8?q?=D0=BC=D0=BE=D0=B4=D1=83=D0=BB=D1=8F=20=D0=B2=20=D0=BF=D1=80?=
 =?UTF-8?q?=D0=B8=D0=BC=D0=B5=D1=80=D0=B5=20common=20mistakes?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 Basic Verilog structures/Common mistakes.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Basic Verilog structures/Common mistakes.md b/Basic Verilog structures/Common mistakes.md
index 7d104cc..d6a1b5d 100644
--- a/Basic Verilog structures/Common mistakes.md	
+++ b/Basic Verilog structures/Common mistakes.md	
@@ -32,7 +32,7 @@ endmodule
 module testbench();
 logic A, B, C;
 
-adder DUT(
+half_adder DUT(
   .A(A),  // <- здесь будет ошибка,
           // т.к. в модуле half_adder нет порта 'A'
   .b(B),