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Andrei Solodovnikov
2024-06-14 11:43:25 +03:00
parent b46352e588
commit 6d0bd328a4
9 changed files with 36 additions and 18 deletions
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Basic Verilog structures/Multiplexors.md
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@@ -223,6 +223,6 @@ assign one_bit_result = bus1024[select];
## Проверь себя
Как, по-вашему, описать на языке SystemVerilog схему, приведённую ниже?
Как описать на языке SystemVerilog следующую схему?
![../.pic/Basic%20Verilog%20structures/multiplexors/fig_05.drawio.svg](../.pic/Basic%20Verilog%20structures/multiplexors/fig_05.drawio.svg)