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ЛР10. Добавление тб для контроллеров
This commit is contained in:
Andrei Solodovnikov
@@ -386,10 +386,10 @@ endmodule
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2. Для запуска симуляции воспользуйтесь [`этой инструкцией`](../../Vivado%20Basics/Run%20Simulation.md).
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3. Перед запуском симуляции убедитесь, что в качестве top-level модуля выбран корректный (`tb_csr`).
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4. Во время симуляции, вы должны прожать "Run All" и убедиться, что в логе есть сообщение о завершении теста!
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4. Внимательно ознакомьтесь с описанием функционального поведения сигналов `irq_controller`, а так же его структурной схемой. В случае возникновения вопросов, проконсультируйтесь с преподавателем.
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5. Реализуйте модуль `irq_controller`. Для этого:
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1. В `Design Sources` проекта с предыдущих лаб, создайте `SystemSystemVerilog`-файл `irq_controller.sv`.
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2. Опишите в нем модуль `irq_controller` с таким же именем и портами, как указано в [задании](#задание).
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4. Внимательно ознакомьтесь с описанием функционального поведения сигналов `interrupt_controller`, а так же его структурной схемой. В случае возникновения вопросов, проконсультируйтесь с преподавателем.
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5. Реализуйте модуль `interrupt_controller`. Для этого:
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1. В `Design Sources` проекта с предыдущих лаб, создайте `SystemSystemVerilog`-файл `interrupt_controller.sv`.
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2. Опишите в нем модуль `interrupt_controller` с таким же именем и портами, как указано в [задании](#задание).
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6. После описания модуля, его необходимо проверить с помощью тестового окружения.
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1. Тестовое окружение находится [здесь](tb_irq.sv).
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2. Для запуска симуляции воспользуйтесь [`этой инструкцией`](../../Vivado%20Basics/Run%20Simulation.md).
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324
Labs/10. Interrupt subsystem/tb_csr.sv
Normal file
324
Labs/10. Interrupt subsystem/tb_csr.sv
Normal file
@@ -0,0 +1,324 @@
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//////////////////////////////////////////////////////////////////////////////////
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// Company: MIET
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// Engineer: Daniil Strelkov
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// Module Name: tb_csr
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// Project Name: RISCV_practicum
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// Target Devices: Nexys A7-100T
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// Description: tb for CSR controller
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//
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//////////////////////////////////////////////////////////////////////////////////
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module tb_csr();
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logic clk_i;
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logic rst_i;
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logic trap_i;
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logic [ 2:0] opcode_i;
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logic [11:0] addr_i;
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logic [31:0] pc_i;
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logic [31:0] mcause_i;
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logic [31:0] rs1_data_i;
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logic [31:0] imm_data_i;
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logic write_enable_i;
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logic [31:0] read_data_o;
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logic [31:0] mie_o;
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logic [31:0] mepc_o;
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logic [31:0] mtvec_o;
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import csr_pkg::*;
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csr_controller dut(.*);
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always #5 clk_i <= ~clk_i;
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int err_count;
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bit not_stopped;
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initial begin
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$display("\n\n===========================\n\nPress button 'Run All' (F3)\n\n===========================\n\n");
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$stop();
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err_count = 0;
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not_stopped = 1;
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clk_i <= 0;
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rst_i <= 1'b1;
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repeat(2)@(posedge clk_i);
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rst_i <= 1'b0;
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end
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initial begin
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opcode_i = '0;
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addr_i = '0;
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pc_i = '0;
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mcause_i = '0;
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rs1_data_i = '0;
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imm_data_i = '0;
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trap_i = '0;
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repeat(4)@(posedge clk_i);
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csrrw();
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csrrs();
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csrrc();
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csrrwi();
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csrrsi();
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csrrci();
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csrr();
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csrw();
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trap();
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$display("Simulation finished. Number of errors: %d", err_count);
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$finish();
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end
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logic [31:0] data_ref;
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logic [31:0] pc_ref;
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logic [31:0] mcause_ref;
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logic [11:0] addr [0:4] = { MIE_ADDR,
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MTVEC_ADDR,
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MSCRATCH_ADDR,
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MEPC_ADDR,
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MCAUSE_ADDR};
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assign pc_ref = write_enable_i ? pc_i : pc_ref;
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assign mcause_ref = write_enable_i ? mcause_i : mcause_ref;
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always_comb begin
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if (write_enable_i)
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case(opcode_i)
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CSR_RW: data_ref <= #1 rs1_data_i;
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CSR_RS: data_ref <= #1 rs1_data_i | read_data_o;
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CSR_RC: data_ref <= #1 ~rs1_data_i & read_data_o;
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CSR_RWI: data_ref <= #1 imm_data_i;
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CSR_RSI: data_ref <= #1 imm_data_i | read_data_o;
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CSR_RCI: data_ref <= #1 ~imm_data_i & read_data_o;
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default: data_ref <= #1 data_ref;
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endcase
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end
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task clear();
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opcode_i <= CSR_RW;
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rs1_data_i <= 0;
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imm_data_i <= 0;
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write_enable_i <= 1;
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@(posedge clk_i);
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write_enable_i <= 0;
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@(posedge clk_i);
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endtask
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//csrrw
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task csrrw();
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trap_i <= 0;
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opcode_i <= CSR_RW;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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end
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endtask
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//csrrs
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task csrrs();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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opcode_i <= CSR_RS;
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addr_i <= addr[i];
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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end
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endtask
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//csrrc
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task csrrc();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RC;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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end
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endtask
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//csrrwi
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task csrrwi();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RWI;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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end
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endtask
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//csrrsi
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task csrrsi();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RSI;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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end
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endtask
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//csrrci
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task csrrci();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RCI;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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check_reg();
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end
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clear();
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end
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endtask
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//csrr
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task csrr();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RS;
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rs1_data_i <= 0;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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check_reg();
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end
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end
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endtask
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//csrw
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task csrw();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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repeat(20) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RW;
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rs1_data_i <= $random;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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check_reg();
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end
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end
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endtask
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//trap
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task trap();
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repeat(100) begin
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opcode_i <= $random;
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addr_i <= MCAUSE_ADDR;
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pc_i <= $random;
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mcause_i <= $random;
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write_enable_i <= 0;
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trap_i <= 1;
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@(posedge clk_i);
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trap_i <= 0;
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@(posedge clk_i);
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check_reg();
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end
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endtask
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task check_reg();
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trap_i <= 0;
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for (int i = 0; i<5; i = i+1) begin
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addr_i <= addr[i];
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opcode_i <= CSR_RS;
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rs1_data_i <= 0;
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imm_data_i <= $random;
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write_enable_i <= 1;
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@(posedge clk_i);
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end
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endtask
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trap_a: assert property (
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@(posedge clk_i) disable iff ( rst_i )
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(trap_i && (addr_i == MCAUSE_ADDR)) |-> ##1 (mepc_o === pc_i) && (read_data_o === mcause_i)
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)else begin
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err_count++;
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$error("\error write/read trap\n");
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end
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csrrw_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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( (opcode_i === CSR_RW) && write_enable_i) |=> (read_data_o === data_ref) and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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)else begin
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err_count++;
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$error("\error write/read csrrw\n");
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end
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csrrs_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((opcode_i === CSR_RS) && write_enable_i) |=> read_data_o === data_ref and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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)else begin
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err_count++;
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$error("\error write/read csrrs\n");
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end
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csrrc_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((opcode_i === CSR_RC) && write_enable_i) |=> read_data_o === data_ref and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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)else begin
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err_count++;
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$error("\error write/read csrrc\n");
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end
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csrrwi_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((opcode_i === CSR_RWI) && write_enable_i) |=> read_data_o === data_ref and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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)else begin
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err_count++;
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$error("\error write/read csrwi\n");
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end
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csrrci_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((opcode_i === CSR_RCI) && write_enable_i ) |=> read_data_o === data_ref and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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)else begin
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err_count++;
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$error("\error write/read csrrci\n");
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end
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csrrsi_a: assert property (
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@(posedge clk_i) disable iff ( rst_i || trap_i )
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((opcode_i === CSR_RSI) && write_enable_i) |=> read_data_o === data_ref and (addr_i === MIE_ADDR) |-> (mie_o === data_ref) and (addr_i === MEPC_ADDR) |-> (mepc_o === data_ref) and (addr_i === MTVEC_ADDR) |-> (mtvec_o === data_ref)
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)else begin
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err_count++;
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$error("\error write/read csrrsi\n");
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end
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endmodule
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411
Labs/10. Interrupt subsystem/tb_irq.sv
Normal file
411
Labs/10. Interrupt subsystem/tb_irq.sv
Normal file
@@ -0,0 +1,411 @@
|
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//////////////////////////////////////////////////////////////////////////////////
|
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// Company: MIET
|
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// Engineer: Daniil Strelkov
|
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|
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// Module Name: tb_irq
|
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// Project Name: RISCV_practicum
|
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// Target Devices: Nexys A7-100T
|
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// Description: tb for interrupt controller
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//
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//////////////////////////////////////////////////////////////////////////////////
|
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module tb_irq();
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logic clk_i;
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logic rst_i;
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logic exception_i;
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logic irq_req_i;
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logic mret_i;
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logic mie_i;
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logic irq_ret_o;
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logic [31:0] irq_cause_o;
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logic irq_o;
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interrupt_controller dut(.*);
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always #5 clk_i <= ~clk_i;
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initial begin
|
||||
$display("\n\n===========================\n\nPress button 'Run All' (F3)\n\n===========================\n\n");
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$stop();
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clk_i <= 0;
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exception_i = '0;
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mret_i = '0;
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irq_req_i = '0;
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mie_i = '0;
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repeat(4)@(posedge clk_i);
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t1();
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t2();
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t3();
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t4();
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t5();
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t6();
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t7();
|
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t8();
|
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t9();
|
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t10();
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t11();
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t12();
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$finish;
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end
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task reset();
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rst_i <= 1'b1;
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@(posedge clk_i);
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@(posedge clk_i);
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rst_i <= 1'b0;
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mret_i = 0;
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exception_i = 0;
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irq_req_i = 0;
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mie_i = 0;
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endtask
|
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logic [1:0] k;
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|
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task t1();
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reset();
|
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@(posedge clk_i);
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mret_i = 0;
|
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exception_i = 0;
|
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irq_req_i = 1;
|
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mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=1) $display("Error: irq_o != 1");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
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@(posedge clk_i);
|
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endtask
|
||||
|
||||
task t2();
|
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reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 0;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
endtask
|
||||
|
||||
task t3();
|
||||
reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
endtask
|
||||
|
||||
task t4();
|
||||
reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 1;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
endtask
|
||||
|
||||
task t5();
|
||||
reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
@(posedge clk_i);
|
||||
mret_i = 1;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=1) $display("Error: irq_ret_o != 1");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
endtask
|
||||
|
||||
task t6();
|
||||
reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 1;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
@(posedge clk_i);
|
||||
mret_i = 1;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
endtask
|
||||
|
||||
task t7();
|
||||
reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 1;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
@(posedge clk_i);
|
||||
mret_i = 1;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
endtask
|
||||
|
||||
task t8();
|
||||
reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 1;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
@(posedge clk_i);
|
||||
mret_i = 1;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 1;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=1) $display("Error: irq_ret_o != 1");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
|
||||
endtask
|
||||
|
||||
task t9();
|
||||
reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
@(posedge clk_i);
|
||||
mret_i = 1;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=1) $display("Error: irq_ret_o != 1");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=1) $display("Error: irq_o != 1");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
endtask
|
||||
|
||||
task t10();
|
||||
reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 1;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
@(posedge clk_i);
|
||||
mret_i = 1;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=1) $display("Error: irq_o != 1");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
endtask
|
||||
|
||||
task t11();
|
||||
reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 1;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
@(posedge clk_i);
|
||||
mret_i = 1;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
endtask
|
||||
|
||||
task t12();
|
||||
reset();
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 1;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
@(posedge clk_i);
|
||||
mret_i = 1;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 1;
|
||||
exception_i = 0;
|
||||
irq_req_i = 0;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=0) $display("Error: irq_o != 0");
|
||||
if (irq_ret_o!=1) $display("Error: irq_ret_o != 1");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
@(posedge clk_i);
|
||||
mret_i = 0;
|
||||
exception_i = 0;
|
||||
irq_req_i = 1;
|
||||
mie_i = 1;
|
||||
#1
|
||||
if (irq_o!=1) $display("Error: irq_o != 1");
|
||||
if (irq_ret_o!=0) $display("Error: irq_ret_o != 0");
|
||||
if (irq_cause_o!=32'h1000_0010) $display("Error: irq_o != 32'h1000_0010");
|
||||
endtask
|
||||
|
||||
endmodule
|
||||
Reference in New Issue
Block a user