From 4caa727f9fbde3a62303afb5bbe281926540543f Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Fri, 4 Oct 2024 19:41:11 +0300 Subject: [PATCH] =?UTF-8?q?=D0=9B=D0=A011.=20=D0=9F=D0=B5=D1=80=D0=B5?= =?UTF-8?q?=D0=B8=D0=BC=D0=B5=D0=BD=D0=BE=D0=B2=D0=B0=D0=BD=D0=B8=D0=B5=20?= =?UTF-8?q?DUT=20=D0=B2=20=D1=82=D0=B1?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../lab_11.tb_processor_system.sv | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Labs/11. Interrupt integration/lab_11.tb_processor_system.sv b/Labs/11. Interrupt integration/lab_11.tb_processor_system.sv index 7f88c54..f937666 100644 --- a/Labs/11. Interrupt integration/lab_11.tb_processor_system.sv +++ b/Labs/11. Interrupt integration/lab_11.tb_processor_system.sv @@ -13,7 +13,7 @@ module lab_11_tb_processor_system(); reg clk; reg rst; - processor_system system( + processor_system DUT( .clk_i(clk), .rst_i(rst) ); @@ -30,16 +30,16 @@ module lab_11_tb_processor_system(); initial begin $display( "\nTest has been started"); - system.irq_req = 0; + DUT.irq_req = 0; rst = 1; #40; rst = 0; repeat(20)@(posedge clk); - system.irq_req = 1; - while(system.irq_ret == 0) begin + DUT.irq_req = 1; + while(DUT.irq_ret == 0) begin @(posedge clk); end - system.irq_req = 0; + DUT.irq_req = 0; repeat(20)@(posedge clk); $display("\n The test is over \n See the internal signals of the module on the waveform \n"); $finish;