From 4be66525d6d13e388572a009c64edc470d2c64c2 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 15 Nov 2023 14:32:42 +0300 Subject: [PATCH] =?UTF-8?q?=D0=A3=D0=B4=D0=B0=D0=BB=D0=B5=D0=BD=D0=B8?= =?UTF-8?q?=D0=B5=20timescale=20=D0=B8=D0=B7=20=D0=B2=D1=81=D0=B5=D1=85=20?= =?UTF-8?q?=D0=BF=D1=80=D0=B5=D0=B4=D0=BE=D1=81=D1=82=D0=B0=D0=B2=D0=BB?= =?UTF-8?q?=D1=8F=D0=B5=D0=BC=D1=8B=D1=85=20=D0=BC=D0=BE=D0=B4=D1=83=D0=BB?= =?UTF-8?q?=D0=B5=D0=B9?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Поскольку студентам не рассказывается что это за конструкция и зачем она используется, они не прописывают таймскейл в своих модулях. Смесь модулей с таймскейлом и без него приводит к появлению множества предупреждений, забивающих лог. --- Labs/01. Adder/board files/nexys_adder.sv | 2 -- Labs/01. Adder/tb_fulladder.sv | 1 - Labs/01. Adder/tb_fulladder32.sv | 1 - Labs/01. Adder/tb_fulladder4.sv | 1 - Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv | 2 -- Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv | 1 - Labs/03. Register file and memory/board files/nexys_rf_riscv.sv | 2 -- Labs/03. Register file and memory/tb_data_mem.sv | 1 - Labs/03. Register file and memory/tb_instr_mem.sv | 1 - Labs/03. Register file and memory/tb_rf_riscv.sv | 1 - .../board files/nexys_cybercobra.sv | 2 -- .../board files/nexys_cybercobra_demo.sv | 2 -- Labs/04. Primitive programmable device/tb_cybercobra.sv | 1 - Labs/05. Main decoder/tb_decoder_riscv.sv | 1 - Labs/06. Datapath/board files/nexys_riscv_unit.sv | 2 -- Labs/06. Datapath/tb_riscv_unit.sv | 1 - Labs/12. Peripheral units/PS2Receiver.v | 2 -- Labs/12. Peripheral units/hex_digits.v | 2 -- Labs/12. Peripheral units/testbench.sv | 1 - Labs/Made-up modules/lab_02.alu.sv | 2 -- 20 files changed, 29 deletions(-) diff --git a/Labs/01. Adder/board files/nexys_adder.sv b/Labs/01. Adder/board files/nexys_adder.sv index 0847b5d..3fe6e1a 100644 --- a/Labs/01. Adder/board files/nexys_adder.sv +++ b/Labs/01. Adder/board files/nexys_adder.sv @@ -1,5 +1,3 @@ -`timescale 1ns / 1ps - module nexys_adder( input CLK100, input resetn, diff --git a/Labs/01. Adder/tb_fulladder.sv b/Labs/01. Adder/tb_fulladder.sv index 66d135e..1804578 100644 --- a/Labs/01. Adder/tb_fulladder.sv +++ b/Labs/01. Adder/tb_fulladder.sv @@ -1,4 +1,3 @@ -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/01. Adder/tb_fulladder32.sv b/Labs/01. Adder/tb_fulladder32.sv index 79b2ea5..152f6b2 100644 --- a/Labs/01. Adder/tb_fulladder32.sv +++ b/Labs/01. Adder/tb_fulladder32.sv @@ -1,4 +1,3 @@ -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/01. Adder/tb_fulladder4.sv b/Labs/01. Adder/tb_fulladder4.sv index f3b7f0d..927c360 100644 --- a/Labs/01. Adder/tb_fulladder4.sv +++ b/Labs/01. Adder/tb_fulladder4.sv @@ -1,4 +1,3 @@ -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv b/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv index 82db55c..0780001 100644 --- a/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv +++ b/Labs/02. Arithmetic-logic unit/board files/nexys_alu.sv @@ -1,5 +1,3 @@ -`timescale 1ns / 1ps - module nexys_alu( input CLK100, input resetn, diff --git a/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv b/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv index 5bb02a3..e490b32 100644 --- a/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv +++ b/Labs/02. Arithmetic-logic unit/tb_miriscv_alu.sv @@ -1,4 +1,3 @@ -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv index 634b1e2..cdec335 100644 --- a/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv +++ b/Labs/03. Register file and memory/board files/nexys_rf_riscv.sv @@ -1,5 +1,3 @@ -`timescale 1ns / 1ps - module nexys_rf_riscv( input CLK100, input resetn, diff --git a/Labs/03. Register file and memory/tb_data_mem.sv b/Labs/03. Register file and memory/tb_data_mem.sv index 282b04d..efb7fb3 100644 --- a/Labs/03. Register file and memory/tb_data_mem.sv +++ b/Labs/03. Register file and memory/tb_data_mem.sv @@ -1,4 +1,3 @@ -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/03. Register file and memory/tb_instr_mem.sv b/Labs/03. Register file and memory/tb_instr_mem.sv index 8ae6722..4297e62 100644 --- a/Labs/03. Register file and memory/tb_instr_mem.sv +++ b/Labs/03. Register file and memory/tb_instr_mem.sv @@ -1,4 +1,3 @@ -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/03. Register file and memory/tb_rf_riscv.sv b/Labs/03. Register file and memory/tb_rf_riscv.sv index a0c55f1..7ec103a 100644 --- a/Labs/03. Register file and memory/tb_rf_riscv.sv +++ b/Labs/03. Register file and memory/tb_rf_riscv.sv @@ -1,4 +1,3 @@ -`timescale 1ns/1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv b/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv index 3e1b09f..27b30fd 100644 --- a/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv +++ b/Labs/04. Primitive programmable device/board files/nexys_cybercobra.sv @@ -1,5 +1,3 @@ -`timescale 1ns / 1ps - module nexys_CYBERcobra_dz( input CLK100, input resetn, diff --git a/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv b/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv index dc3eedc..e0bc145 100644 --- a/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv +++ b/Labs/04. Primitive programmable device/board files/nexys_cybercobra_demo.sv @@ -1,5 +1,3 @@ -`timescale 1ns / 1ps - module nexys_CYBERcobra( input CLK100, input resetn, diff --git a/Labs/04. Primitive programmable device/tb_cybercobra.sv b/Labs/04. Primitive programmable device/tb_cybercobra.sv index 890fddd..12025ea 100644 --- a/Labs/04. Primitive programmable device/tb_cybercobra.sv +++ b/Labs/04. Primitive programmable device/tb_cybercobra.sv @@ -1,4 +1,3 @@ -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/05. Main decoder/tb_decoder_riscv.sv b/Labs/05. Main decoder/tb_decoder_riscv.sv index e581106..59c4936 100644 --- a/Labs/05. Main decoder/tb_decoder_riscv.sv +++ b/Labs/05. Main decoder/tb_decoder_riscv.sv @@ -1,4 +1,3 @@ -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/06. Datapath/board files/nexys_riscv_unit.sv b/Labs/06. Datapath/board files/nexys_riscv_unit.sv index 7049f9a..bfe52b6 100644 --- a/Labs/06. Datapath/board files/nexys_riscv_unit.sv +++ b/Labs/06. Datapath/board files/nexys_riscv_unit.sv @@ -1,5 +1,3 @@ -`timescale 1ns / 1ps - module nexys_riscv_unit( input CLK100, input resetn, diff --git a/Labs/06. Datapath/tb_riscv_unit.sv b/Labs/06. Datapath/tb_riscv_unit.sv index bb3d023..b648a96 100644 --- a/Labs/06. Datapath/tb_riscv_unit.sv +++ b/Labs/06. Datapath/tb_riscv_unit.sv @@ -1,4 +1,3 @@ -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/12. Peripheral units/PS2Receiver.v b/Labs/12. Peripheral units/PS2Receiver.v index 6137099..1c85af2 100644 --- a/Labs/12. Peripheral units/PS2Receiver.v +++ b/Labs/12. Peripheral units/PS2Receiver.v @@ -1,5 +1,3 @@ -`timescale 1ns / 1ps - module PS2Receiver( input clk, input kclk, diff --git a/Labs/12. Peripheral units/hex_digits.v b/Labs/12. Peripheral units/hex_digits.v index 2f51ed0..bf37bfb 100644 --- a/Labs/12. Peripheral units/hex_digits.v +++ b/Labs/12. Peripheral units/hex_digits.v @@ -1,5 +1,3 @@ -`timescale 1ns / 1ps - module hex_digits( input clk_i, rst_i, input [4:0] hex0, // Входной сигнал со значением цифры, выводимой на нулевой (самый правый) индикатор diff --git a/Labs/12. Peripheral units/testbench.sv b/Labs/12. Peripheral units/testbench.sv index aeb10ba..44bf88b 100644 --- a/Labs/12. Peripheral units/testbench.sv +++ b/Labs/12. Peripheral units/testbench.sv @@ -1,4 +1,3 @@ -`timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Company: MIET // Engineer: Nikita Bulavin diff --git a/Labs/Made-up modules/lab_02.alu.sv b/Labs/Made-up modules/lab_02.alu.sv index 601582e..d40813a 100644 --- a/Labs/Made-up modules/lab_02.alu.sv +++ b/Labs/Made-up modules/lab_02.alu.sv @@ -1,5 +1,3 @@ -`timescale 1 ps / 1 ps - (* STRUCTURAL_NETLIST = "yes" *) module alu_riscv (alu_op_i,