From 4b015a63634d375228de7bae7b84ef1270118bc8 Mon Sep 17 00:00:00 2001
From: alexkharl <sasha_xarlamov@mail.ru>
Date: Mon, 12 Feb 2024 11:25:26 +0300
Subject: [PATCH] =?UTF-8?q?Revert=20"Ref(01=5FAdder):=D0=A3=D0=BB=D1=83?=
 =?UTF-8?q?=D1=87=D1=88-=D0=B8=D0=B5=20=D0=BB=D0=BE=D0=B3=D0=B8=D1=80?=
 =?UTF-8?q?=D0=BE=D0=B2=D0=B0=D0=BD=D0=B8=D1=8F"?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

This reverts commit 92147fa3033b3d83bd95907bc0e63b7b3514a54d.
---
 Labs/01. Adder/tb_fulladder.sv   | 12 ++++--------
 Labs/01. Adder/tb_fulladder32.sv | 33 +++++++++++++++++++-------------
 Labs/01. Adder/tb_fulladder4.sv  | 16 ++++++----------
 3 files changed, 30 insertions(+), 31 deletions(-)

diff --git a/Labs/01. Adder/tb_fulladder.sv b/Labs/01. Adder/tb_fulladder.sv
index 1497be9..816d70b 100644
--- a/Labs/01. Adder/tb_fulladder.sv	
+++ b/Labs/01. Adder/tb_fulladder.sv	
@@ -9,10 +9,9 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 module tb_fulladder();
-    timeunit      1ns;
-    timeprecision 1ps;
-    parameter TIME_OPERATION  = 100;
-    parameter TEST_VALUES = 8;
+
+parameter TIME_OPERATION  = 100;
+parameter TEST_VALUES = 8;
 
     wire tb_a_i;
     wire tb_b_i;
@@ -38,16 +37,13 @@ module tb_fulladder();
     assign tb_carry_i = running_line[2];
 
     initial begin
-        $timeformat(-9, 2, " ns");
-
         $display("START simulation of 1-bit fulladder.");
         $display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
-        $display("If you don't see the message then click the button 'Run All'");
         for (i = 0; i < TEST_VALUES; i = i + 1) begin
             running_line = line_dump[i*5+:5];
             #TIME_OPERATION;
         end
-        $display("FINISH simulation, time == %t", $realtime);
+        $display("FINISH simulation");
         $display(
             "Now you should open the waveform window",
             "and visually prove correctness of the design"
diff --git a/Labs/01. Adder/tb_fulladder32.sv b/Labs/01. Adder/tb_fulladder32.sv
index 5859a4a..5070e6c 100644
--- a/Labs/01. Adder/tb_fulladder32.sv	
+++ b/Labs/01. Adder/tb_fulladder32.sv	
@@ -39,25 +39,32 @@ parameter TEST_VALUES = 3000;
     assign sum_dump = running_line[31:0];
     assign carry_o_dump = running_line[32];
 
+`ifdef __debug__
     initial begin
-        $timeformat(-9, 2, " ns");
-
-        $display("START simulation of 32-bit fulladder.");
-        $display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
-        $display("If you don't see the message then click the button 'Run All'");
-        for ( i = 0; i < TEST_VALUES; i = i + 1 ) begin
-            running_line = line_dump[i*98+:98];
-            #TIME_OPERATION;
-            if( (tb_carry_o !== carry_o_dump) || (tb_sum_o !== sum_dump) ) begin
-                $display("ERROR! carry_i = %b; (a)%h + (b)%h = ", tb_carry_i, tb_a_i, tb_b_i, "(carry_o)%b (sum_o)%h;", tb_carry_o, tb_sum_o, " carry_o_dump: %b, sum_dump: %h", carry_o_dump, sum_dump, " time == %t", $realtime);
-                err_count = err_count + 1'b1;
+        $display( "\nStart test: \n\n==========================\nCLICK THE BUTTON 'Run All'\n==========================\n"); $stop();
+        for ( i = 0; i < TEST_VALUES; i = i + 1 )
+            begin
+                running_line = line_dump[i*98+:98];
+                #TIME_OPERATION;
+                if( (tb_carry_o !== carry_o_dump) || (tb_sum_o !== sum_dump) ) begin
+                    $display("ERROR! carry_i = %b; (a)%h + (b)%h = ", tb_carry_i, tb_a_i, tb_b_i, "(carry_o)%b (sum_o)%h;", tb_carry_o, tb_sum_o, " carry_o_dump: %b, sum_dump: %h", carry_o_dump, sum_dump);
+                    err_count = err_count + 1'b1;
+                end
             end
-        end
         $display("Number of errors: %d", err_count);
         if( !err_count )  $display("\nfulladder32 SUCCESS!!!\n");
-        $display("FINISH simulation, time == %t", $realtime);
         $finish();
     end
+`else
+    initial begin
+        for ( i = 0; i < TEST_VALUES; i = i + 1 )
+            begin
+                #TIME_OPERATION;
+                running_line = line_dump[i*98+:98];
+            end
+        $finish();
+    end
+`endif
 initial line_dump = {
 98'h04854d49302257a06d29e93a6,
 98'h2c7c1598c1ae5ec36b8a9d171,
diff --git a/Labs/01. Adder/tb_fulladder4.sv b/Labs/01. Adder/tb_fulladder4.sv
index a247b7e..182c6ee 100644
--- a/Labs/01. Adder/tb_fulladder4.sv	
+++ b/Labs/01. Adder/tb_fulladder4.sv	
@@ -9,8 +9,6 @@
 //////////////////////////////////////////////////////////////////////////////////
 
 module tb_fulladder4();
-    timeunit      1ns;
-    timeprecision 1ps;
 
     parameter TIME_OPERATION  = 100;
     parameter TEST_VALUES = 400;
@@ -42,16 +40,14 @@ module tb_fulladder4();
     assign carry_o_dump = running_line[0];
 
     initial begin
-        $timeformat(-9, 2, " ns");
-
         $display("START simulation of 4-bit fulladder.");
         $display("You should run simmulation until the message 'FINISH simulation' appears in the log.");
-        $display("If you don't see the message then click the button 'Run All'");
-        for ( i = TEST_VALUES-1; i >=0 ; i = i - 1 ) begin
-            running_line = line_dump[i*14+:14];
-            #TIME_OPERATION;
-        end
-        $display("FINISH simulation, time == %t", $realtime);
+        for ( i = TEST_VALUES-1; i >=0 ; i = i - 1 )
+            begin
+                running_line = line_dump[i*14+:14];
+                #TIME_OPERATION;
+            end
+        $display("FINISH simulation");
         $display(
             "Now you should open the waveform window",
             "and visually prove correctness of the design"