From 4aa7ed1be86663b5de0707afe59b3707aab3666d Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 1 Jul 2026 14:33:40 +0300 Subject: [PATCH] =?UTF-8?q?=D0=98=D1=81=D0=BF=D1=80=D0=B0=D0=B2=D0=BB?= =?UTF-8?q?=D0=B5=D0=BD=D0=B8=D0=B5=20=D0=BE=D1=82=D0=BE=D0=B1=D1=80=D0=B0?= =?UTF-8?q?=D0=B6=D0=B5=D0=BD=D0=B8=D1=8F=20svg=20(#164)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- .../assignments/fig_01.drawio.svg | 128 +------- .../assignments/fig_02.drawio.svg | 135 +------- .../assignments/fig_03.drawio.svg | 308 +----------------- .../assignments/fig_14.drawio.svg | 165 +--------- .../Sequential logic/fig_03.drawio.svg | 299 +---------------- 5 files changed, 20 insertions(+), 1015 deletions(-) diff --git a/.pic/Basic Verilog structures/assignments/fig_01.drawio.svg b/.pic/Basic Verilog structures/assignments/fig_01.drawio.svg index 29de791..d848308 100644 --- a/.pic/Basic Verilog structures/assignments/fig_01.drawio.svg +++ b/.pic/Basic Verilog structures/assignments/fig_01.drawio.svg @@ -1,124 +1,4 @@ - - - - - - - -
-
-
-
-
- logic [ - - 31 - - : - - 0 - - ] a,b,c; -
-
-
- - initial begin - -
-
- -
-
-
- - a - - = - - 5 - - ; -
-
-
- - b - - = a; -
-
- - c - - = b; -
-
- - end - -
-
-
-
-
- - - logic [31:0] a,b,c;... - - - - - - - - -
-
-
- - 0ns - -
-
-
- - - 0ns - - - - - - - -
-
-
- - 0ns - -
-
-
- - - 0ns - - - - - - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
logic [31:0] a,b,c;
initial begin
  a = 5;
  b = a;
  c = b;
end
logic [31:0] a,b,c;...
0ns
0ns
0ns
0nsText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Basic Verilog structures/assignments/fig_02.drawio.svg b/.pic/Basic Verilog structures/assignments/fig_02.drawio.svg index 2c24838..836019e 100644 --- a/.pic/Basic Verilog structures/assignments/fig_02.drawio.svg +++ b/.pic/Basic Verilog structures/assignments/fig_02.drawio.svg @@ -1,131 +1,4 @@ - - - - - - - - -
-
-
-
-
- logic [ - - 3 - - - 1 - - : - - 0 - - ] a,b,c; -
-
-
- - initial begin - -
-
- -
-
-
- - // ... - -
-
- - a - - <= - - 5 - - ; -
-
-
- - b - - <= a; -
-
- - c - - <= b; -
-
- - end - -
-
-
-
-
- - - logic [31:0] a,b,c;... - - - - - - - -
-
-
- - 5ns - -
-
-
- - - 5ns - - - - - - - -
-
-
- - 5ns - -
-
-
- - - 5ns - - - - - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
logic [31:0] a,b,c;
initial begin
  // ...
  a <= 5;
  b <= a;
  c <= b;
end
logic [31:0] a,b,c;...
5ns
5ns
5ns
5nsText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg b/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg index 4871d7b..96a5150 100644 --- a/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg +++ b/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg @@ -1,304 +1,4 @@ - - - - - - - -
-
-
-
-
-
-
-
- - module - - - blocking_assignment - - - ( - -
-
- - - - input - - - - - logic - - - a, b - -
-
- - - - output - - - - - logic - - - c, d - -
-
- - ); - -
-
-
-
- - // блокирующее присваивание -
- -
- - always_ff - - - @(posedge clk) begin - -
-
- - - - b = a; - -
-
- -
- -
-
- - c = b; - - - // обновленное значение b - -
-
- -
- -
-
- - d = c; - - - // обновленное значение с - -
-
- - end - -
-
- -
- -
-
- - endmodule - -
-
-
-
-
-
-
-
- - - module blocking_assignment(... - - - - - - - -
-
-
-
-
-
-
-
- - module - - - non - - - bloc - - - king_a - - - ssignment - - - ( - -
-
- - - - input - - - - - logic - - - a, b - -
-
- - - - output - - - - - logic - - - c, d - -
-
- - ); - -
-
-
-
- - // неблокирующее присваивание -
- -
- - always_ff - - - @(posedge clk) begin - -
-
- - - - b <= a; - -
-
- -
- -
-
- - c <= b; - - - // старое значение b - -
-
- -
- -
-
- - d <= c; - - - // старое значение c - -
-
- - end - -
-
- -
- -
-
- - endmodule - -
-
-
-
-
-
-
-
- - - module nonblocking_assignment(... - - - - - - - - - - - - - - - - - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
module blocking_assignment(
  input  logic a, b
  output logic c, d
);

// блокирующее присваивание
always_ff @(posedge clk) begin
  b = a;

  c = b;  // обновленное значение b

  d = c;  // обновленное значение с
end

endmodule
module blocking_assignment(...
module nonblocking_assignment(
  input  logic a, b
  output logic c, d
);

// неблокирующее присваивание
always_ff @(posedge clk) begin
  b <= a;

  c <= b;  // старое значение b

  d <= c;  // старое значение c
end

endmodule
module nonblocking_assignment(...Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg b/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg index 76320dc..bd08cf5 100644 --- a/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg +++ b/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg @@ -1,161 +1,4 @@ - - - - - - - -
-
-
-
-
- logic [ - - 3 - - - 1 - - : - - 0 - - ] a,b,c; -
-
-
- - always_comb begin - -
-
-
- - temp - - <= a | b; -
-
-
- - d - - <= c & temp; -
-
- - end - -
-
-
-
-
-
- - - logic [31:0] a,b,c;... - - - - - - - - - - -
-
-
- - 5ns - -
-
-
- - - 5ns - - - - - - - -
-
-
- - 5ns - -
-
-
- - - 5ns - - - - - - - - - - - -
-
-
- - - Первый проход блока always - - -
-
-
- - - Первый проход блока always - - - - - - - - - -
-
-
- - - Второй проход блока always - - -
-
-
- - - Второй проход блока always - - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
logic [31:0] a,b,c;
always_comb begin
  temp <= a | b;
  d    <= c & temp;
end
logic [31:0] a,b,c;...
5ns
5ns
5ns
5ns
Первый проход блока always
Первый проход блока always
Второй проход блока always
Второй проход блока alwaysText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Introduction/Sequential logic/fig_03.drawio.svg b/.pic/Introduction/Sequential logic/fig_03.drawio.svg index c320f6d..83bced1 100644 --- a/.pic/Introduction/Sequential logic/fig_03.drawio.svg +++ b/.pic/Introduction/Sequential logic/fig_03.drawio.svg @@ -1,295 +1,4 @@ - - - - - - - -
-
-
- RS-триггер -
-
-
- - - RS-триггер - - - - - - - - - - - - - - - - - - - - - - - - - -
-
-
- Q -
-
-
- - - Q - - - - - - - -
-
-
- Q̅ -
-
-
- - - Q̅ - - - - - - - -
-
-
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-
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- - - S - - - - - - - -
-
-
- R -
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- - - R - - - - - - - -
-
-
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - Входы - - - - - Выходы - - -
- S - - - R - - - - Q - - n - - - - Q - - n+1 - -
- 		- Q̅ - - n+1 - -
-
- 0 - - - 0 - - - - 0 - - - - 0 - - - - 1 - -
- 0 - - - 0 - - - - 1 - - - 1 - - - 0 - -
- 0 - - - 1 - - - x - - - 0 - - - - 1 - -
- 1 - - - 0 - - - - x - - - - 1 - - - - 0 - -
- 1 - - 1 - - x - - 0 - - 0 -
-
-
-
- - - ВходыВыходы   S     R     Qn  Qn+1... - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
RS-триггер
RS-триггер
Q
Q
Q̅
Q̅
S
S
R
R
ВходыВыходы
   S     R     Qn  Qn+1
Q̅n+1
00001
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01x01
10x10
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ВходыВыходы   S     R     Qn  Qn+1...Text is not SVG - cannot display \ No newline at end of file