diff --git a/.pic/Basic Verilog structures/assignments/fig_01.drawio.svg b/.pic/Basic Verilog structures/assignments/fig_01.drawio.svg index 29de791..d848308 100644 --- a/.pic/Basic Verilog structures/assignments/fig_01.drawio.svg +++ b/.pic/Basic Verilog structures/assignments/fig_01.drawio.svg @@ -1,124 +1,4 @@ - - - - - - - -
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- logic [ - - 31 - - : - - 0 - - ] a,b,c; -
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- - initial begin - -
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- - a - - = - - 5 - - ; -
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- - b - - = a; -
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- - c - - = b; -
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- - end - -
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- - - logic [31:0] a,b,c;... - - - - - - - - -
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logic [31:0] a,b,c;
initial begin
  a = 5;
  b = a;
  c = b;
end
logic [31:0] a,b,c;...
0ns
0ns
0ns
0nsText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Basic Verilog structures/assignments/fig_02.drawio.svg b/.pic/Basic Verilog structures/assignments/fig_02.drawio.svg index 2c24838..836019e 100644 --- a/.pic/Basic Verilog structures/assignments/fig_02.drawio.svg +++ b/.pic/Basic Verilog structures/assignments/fig_02.drawio.svg @@ -1,131 +1,4 @@ - - - - - - - - -
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- logic [ - - 3 - - - 1 - - : - - 0 - - ] a,b,c; -
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- - initial begin - -
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- - // ... - -
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- - a - - <= - - 5 - - ; -
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- - b - - <= a; -
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- - c - - <= b; -
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- - end - -
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- - - logic [31:0] a,b,c;... - - - - - - - -
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logic [31:0] a,b,c;
initial begin
  // ...
  a <= 5;
  b <= a;
  c <= b;
end
logic [31:0] a,b,c;...
5ns
5ns
5ns
5nsText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg b/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg index 4871d7b..96a5150 100644 --- a/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg +++ b/.pic/Basic Verilog structures/assignments/fig_03.drawio.svg @@ -1,304 +1,4 @@ - - - - - - - -
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- - module - - - blocking_assignment - - - ( - -
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- - - - input - - - - - logic - - - a, b - -
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- - - - output - - - - - logic - - - c, d - -
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- - ); - -
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- - // блокирующее присваивание -
- -
- - always_ff - - - @(posedge clk) begin - -
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- - - - b = a; - -
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- -
- -
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- - c = b; - - - // обновленное значение b - -
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- -
- -
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- - d = c; - - - // обновленное значение с - -
-
- - end - -
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- -
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- - endmodule - -
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- - - module blocking_assignment(... - - - - - - - -
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- - module - - - non - - - bloc - - - king_a - - - ssignment - - - ( - -
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- - - - output - - - - - logic - - - c, d - -
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- - ); - -
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- - // неблокирующее присваивание -
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- - always_ff - - - @(posedge clk) begin - -
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- - - - b <= a; - -
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- -
- -
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- - c <= b; - - - // старое значение b - -
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- -
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- - d <= c; - - - // старое значение c - -
-
- - end - -
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- -
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- - endmodule - -
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- - - module nonblocking_assignment(... - - - - - - - - - - - - - - - - - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
module blocking_assignment(
  input  logic a, b
  output logic c, d
);

// блокирующее присваивание
always_ff @(posedge clk) begin
  b = a;

  c = b;  // обновленное значение b

  d = c;  // обновленное значение с
end

endmodule
module blocking_assignment(...
module nonblocking_assignment(
  input  logic a, b
  output logic c, d
);

// неблокирующее присваивание
always_ff @(posedge clk) begin
  b <= a;

  c <= b;  // старое значение b

  d <= c;  // старое значение c
end

endmodule
module nonblocking_assignment(...Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg b/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg index 76320dc..bd08cf5 100644 --- a/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg +++ b/.pic/Basic Verilog structures/assignments/fig_14.drawio.svg @@ -1,161 +1,4 @@ - - - - - - - -
-
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- logic [ - - 3 - - - 1 - - : - - 0 - - ] a,b,c; -
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- - always_comb begin - -
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- - temp - - <= a | b; -
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- - d - - <= c & temp; -
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- - end - -
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logic [31:0] a,b,c;
always_comb begin
  temp <= a | b;
  d    <= c & temp;
end
logic [31:0] a,b,c;...
5ns
5ns
5ns
5ns
Первый проход блока always
Первый проход блока always
Второй проход блока always
Второй проход блока alwaysText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Introduction/Sequential logic/fig_03.drawio.svg b/.pic/Introduction/Sequential logic/fig_03.drawio.svg index c320f6d..83bced1 100644 --- a/.pic/Introduction/Sequential logic/fig_03.drawio.svg +++ b/.pic/Introduction/Sequential logic/fig_03.drawio.svg @@ -1,295 +1,4 @@ - - - - - - - -
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- RS-триггер -
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- - Входы - - - - - Выходы - - -
- S - - - R - - - - Q - - n - - - - Q - - n+1 - -
- 		- Q̅ - - n+1 - -
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- 0 - - - 0 - - - - 0 - - - - 0 - - - - 1 - -
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ВходыВыходы   S     R     Qn  Qn+1...Text is not SVG - cannot display \ No newline at end of file