MPSU/APS
1
0
Fork 0
mirror of https://github.com/MPSU/APS.git synced 2025-09-16 01:30:10 +00:00
Code Issues Packages Projects Releases Wiki Activity

ЛР12. Добавление оставшихся методических материалов

Browse Source
This commit is contained in:
Andrei Solodovnikov
2023-11-28 00:50:50 +03:00
parent 057c5fe75f
commit 2765ff3aff
20 changed files with 2747 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
Labs/12. Peripheral units/sys_clk_rst_gen.sv
View File

@@ -10,11 +10,11 @@ module sys_clk_rst_gen#(
);
logic [1:0] ex_arstn_buf;
logic [1:0] sys_rstn_buf;
logic [DIV_WIDTH-1:0] sys_rstn_buf;
logic ex_arstn_buffered;
assign ex_arstn_buffered = ex_arstn_buf[1];
assign sys_reset_o = !sys_rstn_buf[1];
assign sys_reset_o = !sys_rstn_buf[DIV_WIDTH-1];
always_ff @(posedge ex_clk_i or negedge ex_areset_n_i) begin
if(!ex_areset_n_i) begin
@@ -32,7 +32,7 @@ always_ff @(posedge ex_clk_i or negedge ex_arstn_buffered) begin
cnt <= 0;
clk_div <= 0;
end else if ( cnt == 0 ) begin
cnt <= div_i;
cnt <= div_i-1;
clk_div <= !clk_div;
end else begin
cnt <= cnt - 1;
@@ -46,7 +46,7 @@ always_ff @(posedge sys_clk_o or negedge ex_arstn_buffered) begin
sys_rstn_buf <= 2'b0;
end
else begin
sys_rstn_buf <= {sys_rstn_buf[0], 1'b1};
sys_rstn_buf <= {sys_rstn_buf[DIV_WIDTH-2:0], 1'b1};
end
end