diff --git a/.pic/Labs/lab_02_alu/fig_02.drawio.svg b/.pic/Labs/lab_02_alu/fig_02.drawio.svg index 200761d..b887464 100644 --- a/.pic/Labs/lab_02_alu/fig_02.drawio.svg +++ b/.pic/Labs/lab_02_alu/fig_02.drawio.svg @@ -1,4 +1,4 @@ -
       11            10              01            00        
11            10              01            00...
+
+
     1           0
     1           0
A
A
AluControl
AluControl
B
B
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
2
2
N
N
Result
Result
Carryout
CarryoutAssets
ALUControl2:0
ALUControl2:0
Операция
Операция
00
00
Сложение
Сложение
01
01
Вычитание
Вычитание
10
10
Логическое И
Логическое И
11
11
Логическое ИЛИ
Логическое ИЛИ
1
1
Sum
Sum
[0]
[0] \ No newline at end of file +
       11            10              01            00        
11            10              01            00...
+
+
     1           0
     1           0
A
A
AluControl
AluControl
B
B
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
N
2
2
N
N
Result
Result
Carryout
CarryoutAssets
ALUControl2:0
ALUControl2:0
Operation
Operation
00
00
Addition
Addition
01
01
Subtraction
Subtraction
10
10
Logical AND
Logical AND
11
11
Logical OR
Logical OR
1
1
Sum
Sum
[0]
[0]Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_02_alu/fig_03.drawio.svg b/.pic/Labs/lab_02_alu/fig_03.drawio.svg index 0f5ba04..134af21 100644 --- a/.pic/Labs/lab_02_alu/fig_03.drawio.svg +++ b/.pic/Labs/lab_02_alu/fig_03.drawio.svg @@ -1,4 +1,4 @@ -
1
0
0
1
1
0
1
0
0
0
1
1
0
1
0
0
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
1
0

Исходное число

Результат сдвига

Исходное число

Результат сдвига

 \ No newline at end of file +
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0

Original number

Original number

Shift result

Shift result

Original number

Original number

Shift result

Shift resultText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_02_alu/fig_04.drawio.svg b/.pic/Labs/lab_02_alu/fig_04.drawio.svg index 041b143..b885e7b 100644 --- a/.pic/Labs/lab_02_alu/fig_04.drawio.svg +++ b/.pic/Labs/lab_02_alu/fig_04.drawio.svg @@ -1,4 +1,4 @@ -
1
0
0
1
1
0
1
0
0
0
1
1
0
1
0
0
0
1
0
0
1
1
0
1
0
1
1
0
0
1
1
0
1

Исходное число

Результат сдвига

Исходное число

Результат сдвига

 \ No newline at end of file +
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1

Original number

Original number

Shift result

Shift result

Original number

Original number

Shift result

Shift resultText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_03_memory/fig_03.drawio.svg b/.pic/Labs/lab_03_memory/fig_03.drawio.svg index 3e4efb3..dd064b8 100644 --- a/.pic/Labs/lab_03_memory/fig_03.drawio.svg +++ b/.pic/Labs/lab_03_memory/fig_03.drawio.svg @@ -1,478 +1,4 @@ - - - - - - - - - -
-
-
- - mem - -
-
-
- - - mem - - - - - - - - - -
-
-
- - - 32'hdead_beaf - - -
-
-
- - - 32'hdead_beaf - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - -
-
-
- ADDR -
-
-
- - - ADDR - - - - - - - -
-
-
- WE -
-
-
- - - WE - - - - - - - -
-
-
- WD -
-
-
- - - WD - - - - - - - - - - - -
-
-
-

- - 0 -
- 1 -
- 2 -
- -

-
-
-
- - - 0... - - - - - - - -
-
-
- RD -
-
-
- - - RD - - - - - - - -
-
-
-

- - clk_i - -

-
-
-
- - - clk_i - - - - - - - - - -
-
-
- - - 32 -
- - -
-
-
- - - 32 - - - - - - - - -
-
-
- - - 32 -
- - -
-
-
- - - 32 - - - - - - - - -
-
-
- REQ -
-
-
- - - REQ - - - - - - - -
-
-
- EN -
-
-
- - - EN - - - - - - - - - - - -
-
-
- - - 32'hfa11_1eaf - - -
-
-
- - - 32'hfa11_1eaf - - - - - - - -
-
-
- - - 32 -
- - -
-
-
- - - 32 - - - - - - - - - -
-
-
- - - 32 -
- - -
-
-
- - - 32 - - - - - - - - - - - -
-
-
-

- - clk_i - -

-
-
-
- - - clk_i - - - - - - - -
-
-
- - mem_req_i - -
-
-
- - - mem_req_i - - - - - - - -
-
-
- write_data_i -
-
-
- - - write_data_i - - - - - - - -
-
-
- write_enable_i -
-
-
- - - write_enable_i - - - - - - - -
-
-
- addr_i -
-
-
- - - addr_i - - - - - - - -
-
-
- read_data_o -
-
-
- - - read_data_o - - - - - - - - -
-
-
- тут будет логика управления мультиплексором -
-
-
- - - тут будет логика управления мультиплексором - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
mem
mem
32'hdead_beaf
32'hdead_beaf
RD
RD
ADDR
ADDR
WE
WE
WD
WD

0
1
2

0...
RD
RD

clk_i

clk_i
32
32
32
32
REQ
REQ
EN
EN
32'hfa11_1eaf
32'hfa11_1eaf
32
32
32
32

clk_i

clk_i
mem_req_i
mem_req_i
write_data_i
write_data_i
write_enable_i
write_enable_i
addr_i
addr_i
read_data_o
read_data_o
Here will be the multiplexer control logic
Here will be th...Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_03_memory/fig_03.png b/.pic/Labs/lab_03_memory/fig_03.png index 79193bd..72aa4e2 100644 Binary files a/.pic/Labs/lab_03_memory/fig_03.png and b/.pic/Labs/lab_03_memory/fig_03.png differ diff --git a/.pic/Labs/lab_03_memory/fig_03.xlsx b/.pic/Labs/lab_03_memory/fig_03.xlsx index ae6533e..005c553 100644 Binary files a/.pic/Labs/lab_03_memory/fig_03.xlsx and b/.pic/Labs/lab_03_memory/fig_03.xlsx differ diff --git a/.pic/Labs/lab_04_cybercobra/ppd_0.drawio.svg b/.pic/Labs/lab_04_cybercobra/ppd_0.drawio.svg index 26858ad..d7c5cdc 100644 --- a/.pic/Labs/lab_04_cybercobra/ppd_0.drawio.svg +++ b/.pic/Labs/lab_04_cybercobra/ppd_0.drawio.svg @@ -1,4 +1,4 @@ -
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
clk_i
clk_i
rst_i
rst_i
,
,
— входы модуля
— входы модуля
+
+
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
1'b1
1'b1
32
32Text is not SVG - cannot display \ No newline at end of file +
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
clk_i
clk_i
rst_i
rst_i
,
,
— module inputs
— module inputs
+
+
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
1'b1
1'b1
32
32Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_04_cybercobra/ppd_1.drawio.svg b/.pic/Labs/lab_04_cybercobra/ppd_1.drawio.svg index eed9042..690f5d7 100644 --- a/.pic/Labs/lab_04_cybercobra/ppd_1.drawio.svg +++ b/.pic/Labs/lab_04_cybercobra/ppd_1.drawio.svg @@ -1,4 +1,4 @@ -
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
clk_i
clk_i
rst_i
rst_i
,
,
— входы модуля
— входы модуля
+
+
[22:18]
[22:...
[17:13]
[17:...
[4:0]
[4:...
[27:23]
[27:...
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
1'b1
1'b1
32
32Text is not SVG - cannot display \ No newline at end of file +
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
clk_i
clk_i
rst_i
rst_i
,
,
— module inputs
— module inputs
+
+
[22:18]
[22:...
[17:13]
[17:...
[4:0]
[4:...
[27:23]
[27:...
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
1'b1
1'b1
32
32Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_04_cybercobra/ppd_2.drawio.svg b/.pic/Labs/lab_04_cybercobra/ppd_2.drawio.svg index 3a1e59b..cff7b25 100644 --- a/.pic/Labs/lab_04_cybercobra/ppd_2.drawio.svg +++ b/.pic/Labs/lab_04_cybercobra/ppd_2.drawio.svg @@ -1,4 +1,4 @@ -
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
1
1
23
23
32
32
0
0
SE
SE
clk_i
clk_i
rst_i
rst_i
sw_i
sw_i
,
,
,
,
— входы модуля
— входы модуля
SE
SE
— знаковое расширение
— знаковое расширение
+
+
[22:18]
[22:...
[17:13]
[17:...
[4:0]
[4:...
[27:23]
[27:...
[27:5]
[27...
[28]
[28]
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
1'b1
1'b1
32
32Text is not SVG - cannot display \ No newline at end of file +
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
1
1
23
23
32
32
0
0
SE
SE
clk_i
clk_i
rst_i
rst_i
sw_i
sw_i
,
,
,
,
— module inputs
— module inputs
SE
SE
— sign extension
— sign extension
+
+
[22:18]
[22:...
[17:13]
[17:...
[4:0]
[4:...
[27:23]
[27:...
[27:5]
[27...
[28]
[28]
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
1'b1
1'b1
32
32Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_04_cybercobra/ppd_3.drawio.svg b/.pic/Labs/lab_04_cybercobra/ppd_3.drawio.svg index b28dfb4..b417021 100644 --- a/.pic/Labs/lab_04_cybercobra/ppd_3.drawio.svg +++ b/.pic/Labs/lab_04_cybercobra/ppd_3.drawio.svg @@ -1,4 +1,4 @@ -
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
23
23
32
32
SE
SE
clk_i
clk_i
rst_i
rst_i
sw_i
sw_i
,
,
,
,
— входы модуля
— входы модуля
out_o
out_o
— выход модуля
— выход модуля
SE
SE
— знаковое расширение
— знаковое расширение
{[12:5],00}
{[12:5...
— объединение 8 бит инструкции с
     двумя нулевыми битами
— объединение 8 бит инструкции с...
2
2
out_o
out_o
32
32
+
+
[22:18]
[22:...
[17:13]
[17:...
[4:0]
[4:...
[27:23]
[27:...
[27:5]
[27...
[29:28]
[29:...
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
1'b1
1'b1
2
2
1
1
0
0
SE
SE
32
32
16
16
3
3
32'd0
32'd0
32
32
sw_i
sw_iText is not SVG - cannot display \ No newline at end of file +
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
23
23
32
32
SE
SE
clk_i
clk_i
rst_i
rst_i
sw_i
sw_i
,
,
,
,
— module inputs
— module inputs
out_o
out_o
— module output
— module output
SE
SE
— sign extension
— sign extension
{[12:5],00}
{[12:5...
— concatenation of the 8 instruction         bits with two zero bits
— concatenation of the 8 instruction...
2
2
out_o
out_o
32
32
+
+
[22:18]
[22:...
[17:13]
[17:...
[4:0]
[4:...
[27:23]
[27:...
[27:5]
[27...
[29:28]
[29:...
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
1'b1
1'b1
2
2
1
1
0
0
SE
SE
32
32
16
16
3
3
32'd0
32'd0
32
32
sw_i
sw_iText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_04_cybercobra/ppd_4.drawio.svg b/.pic/Labs/lab_04_cybercobra/ppd_4.drawio.svg index 3d2bdfd..ca59b07 100644 --- a/.pic/Labs/lab_04_cybercobra/ppd_4.drawio.svg +++ b/.pic/Labs/lab_04_cybercobra/ppd_4.drawio.svg @@ -1,4 +1,4 @@ -
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
23
23
32
32
0
0
1
1
[30]
[...
32
32
10
10
{[12:5],2'b0}
{[12:5],2'b...
SE
SE
clk_i
clk_i
rst_i
rst_i
sw_i
sw_i
,
,
,
,
— входы модуля
— входы модуля
out_o
out_o
— выход модуля
— выход модуля
SE
SE
— знаковое расширение
— знаковое расширение
{[12:5],00}
{[12:5...
— объединение 8 бит инструкции с
     двумя нулевыми битами
— объединение 8 бит инструкции с...
2
2
out_o
out_o
32
32
SE
SE
+
+
[22:18]
[22:...
[17:13]
[17:...
[4:0]
[4:...
[27:23]
[27:...
[27:5]
[27...
[29:28]
[29:...
[30]
[30]
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
2
2
1
1
0
0
SE
SE
32
32
16
16
3
3
32'd0
32'd0
32
32
sw_i
sw_iText is not SVG - cannot display \ No newline at end of file +
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
23
23
32
32
0
0
1
1
[30]
[...
32
32
10
10
{[12:5],2'b0}
{[12:5],2'b...
SE
SE
clk_i
clk_i
rst_i
rst_i
sw_i
sw_i
,
,
,
,
— module inputs
— module inputs
out_o
out_o
— module output
— module output
SE
SE
— sign extension
— sign extension
{[12:5],00}
{[12:5...
— concatenation of the 8 instruction         bits with two zero bits
— concatenation of the 8 instruction...
2
2
out_o
out_o
32
32
SE
SE
+
+
[22:18]
[22:...
[17:13]
[17:...
[4:0]
[4:...
[27:23]
[27:...
[27:5]
[27...
[29:28]
[29:...
[30]
[30]
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
2
2
1
1
0
0
SE
SE
32
32
16
16
3
3
32'd0
32'd0
32
32
sw_i
sw_iText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_04_cybercobra/ppd_5.drawio.svg b/.pic/Labs/lab_04_cybercobra/ppd_5.drawio.svg index bfd236a..10f1f30 100644 --- a/.pic/Labs/lab_04_cybercobra/ppd_5.drawio.svg +++ b/.pic/Labs/lab_04_cybercobra/ppd_5.drawio.svg @@ -1,4 +1,4 @@ -
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
2
2
1
1
23
23
32
32
0
0
sw_i
sw_i
0
0
1
1
[30]
[...
[31]
[...
32
32
10
10
{[12:5],2'b0}
{[12:5],2'b...
SE
SE
32
32
16
16
SE
SE
clk_i
clk_i
rst_i
rst_i
sw_i
sw_i
,
,
,
,
— входы модуля
— входы модуля
out_o
out_o
— выход модуля
— выход модуля
SE
SE
— знаковое расширение
— знаковое расширение
{[12:5],00}
{[12:5...
— объединение 8 бит инструкции с
     двумя нулевыми битами
— объединение 8 бит инструкции с...
3
3
2
2
32'd0
32'd0
out_o
out_o
32
32
SE
SE
+
+
[22:18]
[22:...
[17:13]
[17:...
[4:0]
[4:...
[27:23]
[27:...
[27:5]
[27...
[29:28]
[29:...
[30]
[30]
[31]
[31]
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
32
32Text is not SVG - cannot display \ No newline at end of file +
ALU
ALU
Register
File
Register...
RD1
RD1
RD2
RD2
WE
WE
clk_i
clk_i
RA1
RA1
RA2
RA2
WA
WA
WD
WD
32'd4
32'd4
32
32
32
32
32
32
5
5
5
5
5
5
32
32
32
32
32
32
5
5
2
2
1
1
23
23
32
32
0
0
sw_i
sw_i
0
0
1
1
[30]
[...
[31]
[...
32
32
10
10
{[12:5],2'b0}
{[12:5],2'b...
SE
SE
32
32
16
16
SE
SE
clk_i
clk_i
rst_i
rst_i
sw_i
sw_i
,
,
,
,
— module inputs
— module inputs
out_o
out_o
— module output
— module output
SE
SE
— sign extension
— sign extension
{[12:5],00}
{[12:5...
— concatenation of the 8 instruction         bits with two zero bits
— concatenation of the 8 instruction...
3
3
2
2
32'd0
32'd0
out_o
out_o
32
32
SE
SE
+
+
[22:18]
[22:...
[17:13]
[17:...
[4:0]
[4:...
[27:23]
[27:...
[27:5]
[27...
[29:28]
[29:...
[30]
[30]
[31]
[31]
Instruction memory
Instruction memo...
32
32
RD
RD
RA
RA
PC
PC
clk_i
clk_i
rst_i
rst_i
32
32Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_05_decoder/rv32i_summary.png b/.pic/Labs/lab_05_decoder/rv32i_summary.png index a909545..79f962a 100644 Binary files a/.pic/Labs/lab_05_decoder/rv32i_summary.png and b/.pic/Labs/lab_05_decoder/rv32i_summary.png differ diff --git a/.pic/Labs/lab_05_decoder/rv32i_summary.xlsx b/.pic/Labs/lab_05_decoder/rv32i_summary.xlsx index b02eeaa..e7207a7 100644 Binary files a/.pic/Labs/lab_05_decoder/rv32i_summary.xlsx and b/.pic/Labs/lab_05_decoder/rv32i_summary.xlsx differ diff --git a/.pic/Labs/lab_06_main_memory/fig_01.png b/.pic/Labs/lab_06_main_memory/fig_01.png index bf40a6a..72aa4e2 100644 Binary files a/.pic/Labs/lab_06_main_memory/fig_01.png and b/.pic/Labs/lab_06_main_memory/fig_01.png differ diff --git a/.pic/Labs/lab_07_dp/fig_01.drawio.svg b/.pic/Labs/lab_07_dp/fig_01.drawio.svg index 7b3af18..cdb830d 100644 --- a/.pic/Labs/lab_07_dp/fig_01.drawio.svg +++ b/.pic/Labs/lab_07_dp/fig_01.drawio.svg @@ -1,4 +1,4 @@ -

Main
Decoder

Main...

flag

flag
Register
File
Register...
imm_S
imm_S
imm_U
imm_U
4
4
0
0
RD1
RD1
RD2
RD2
gpr_we
gpr_we
WE
WE

clk_i

clk_i
wb_sel
wb_sel
 mem_size
 mem_size
mem_we
mem_we
alu_op
alu_op
b_sel
b_sel
a_sel
a_sel
jal
jal
b
b
instr
instr
RA1
RA1
RA2
RA2
WA
WA
WD
WD
[19:15]
[19:15]
[24:20]
[24:20]
[11:07]
[11:07]
[31:20]
[31:20]
[31:12], 12'h000
[31:12], 12'h000
[31:25][11:7]
[31:25][11:7]
[31][19:12][20][30:21],1'b0
[31][19:12][20][30:21],1'b0
[31][7][30:25][11:8],1'b0
[31][7][30:25][11:8],1'b0
imm_J
imm_J
imm_B
imm_B
4
4
PC
PC

clk_i

clk_i

rst_i

rst_i

imm_I

imm_I
+
+
ALU
ALU
SE
SE
SE
SE
+
+
mem_wd_o
mem_wd_o
instr_i
instr_i
mem_addr_o
mem_addr_o
instr_addr_o
instr_addr_o
mem_rd_i
mem_rd_i
mem_we_o
mem_we_o
mem_size_o
mem_size_o
instr_addr_o
instr_addr_o

instr_i

instr_i

mem_addr_o

mem_addr_o
mem_we_o
mem_we_o

mem_size_o

mem_size_o

rst_i

rst_i

clk_i

clk_i
SE
SE

0

1

0...

0

1

0...

0

1

0...

1

0

1...

flag

flag
RD1
RD1

32
/

32...

32
/

32...

32
/

32...

32
/

32...

32
/

32...

12
/

12...

12
/

12...

21
/

21...

13
/

13...

32
/

32...
не подключен
не подключен
SE
SE
mem_req 
mem_req 

mem_req_o

mem_req_o

imm_I

imm_I
— входные сигналы
— входные сигналы
— выходные сигналы
— выходные сигналы
mem_req_o
mem_req_o

imm_I

imm_I
RD1
RD1

flag

flag
— провода, разорванные        для удобства                    отображения схемы
— провода, разорванные        для удобства...
PC
PC
PC
PC

0
1
2
3
4

0...

0
1
2

0...
32
32
stall_i
stall_i
stall_i
stall_i

32
/

32...
2
2
3
3
3
3
5
5
mem_wd_o
mem_wd_o
mem_rd_i
mem_rd_i
wb_data
wb_data
wb_data
wb_data
wb_data
wb_data
32
32
PC
PC
stall_i
stall_i
{[31:1],1'b0}
{[31:1],1'b0}
не подключен
не подключен
не подключен
не подключен
не подключен
не подключен
 mret
 mret
 illegal_instr
 illegal_instr
 csr_we
 csr_we
 csr_op
 csr_op
jalr
jalr
2
2Text is not SVG - cannot display \ No newline at end of file +

Main
Decoder

Main...

flag

flag
Register
File
Register...
imm_S
imm_S
imm_U
imm_U
4
4
0
0
RD1
RD1
RD2
RD2
gpr_we
gpr_we
WE
WE

clk_i

clk_i
wb_sel
wb_sel
 mem_size
 mem_size
mem_we
mem_we
alu_op
alu_op
b_sel
b_sel
a_sel
a_sel
jal
jal
b
b
instr
instr
RA1
RA1
RA2
RA2
WA
WA
WD
WD
[19:15]
[19:15]
[24:20]
[24:20]
[11:07]
[11:07]
[31:20]
[31:20]
[31:12], 12'h000
[31:12], 12'h000
[31:25][11:7]
[31:25][11:7]
[31][19:12][20][30:21],1'b0
[31][19:12][20][30:21],1'b0
[31][7][30:25][11:8],1'b0
[31][7][30:25][11:8],1'b0
imm_J
imm_J
imm_B
imm_B
4
4
PC
PC

clk_i

clk_i

rst_i

rst_i

imm_I

imm_I
+
+
ALU
ALU
SE
SE
SE
SE
+
+
mem_wd_o
mem_wd_o
instr_i
instr_i
mem_addr_o
mem_addr_o
instr_addr_o
instr_addr_o
mem_rd_i
mem_rd_i
mem_we_o
mem_we_o
mem_size_o
mem_size_o
instr_addr_o
instr_addr_o

instr_i

instr_i

mem_addr_o

mem_addr_o
mem_we_o
mem_we_o

mem_size_o

mem_size_o

rst_i

rst_i

clk_i

clk_i
SE
SE

0

1

0...

0

1

0...

0

1

0...

1

0

1...

flag

flag
RD1
RD1

32
/

32...

32
/

32...

32
/

32...

32
/

32...

32
/

32...

12
/

12...

12
/

12...

21
/

21...

13
/

13...

32
/

32...
not connected
not connected
SE
SE
mem_req 
mem_req 

mem_req_o

mem_req_o

imm_I

imm_I
— input signals
— input signals
— output signals
— output signals
mem_req_o
mem_req_o

imm_I

imm_I
RD1
RD1

flag

flag
— wires broken for                    readability
— wires broken for...
PC
PC
PC
PC

0
1
2
3
4

0...

0
1
2

0...
32
32
stall_i
stall_i
stall_i
stall_i

32
/

32...
2
2
3
3
3
3
5
5
mem_wd_o
mem_wd_o
mem_rd_i
mem_rd_i
wb_data
wb_data
wb_data
wb_data
wb_data
wb_data
32
32
PC
PC
stall_i
stall_i
{[31:1],1'b0}
{[31:1],1'b0}
not connected
not connected
not connected
not connected
not connected
not connected
 mret
 mret
 illegal_instr
 illegal_instr
 csr_we
 csr_we
 csr_op
 csr_op
jalr
jalr
2
2Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_07_dp/fig_02.drawio.svg b/.pic/Labs/lab_07_dp/fig_02.drawio.svg index d5d4acf..3cba745 100644 --- a/.pic/Labs/lab_07_dp/fig_02.drawio.svg +++ b/.pic/Labs/lab_07_dp/fig_02.drawio.svg @@ -1,829 +1,4 @@ - - - - - - - - -
-
-
- - Core -
-
- -
-
-
- - - Core... - - - - - - - -
-
-
- - RST - -
-
-
- - - RST - - - - - - - -
-
-
- MEM_RD -
-
-
- - - MEM_RD - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - - - -
-
-
- - Instruction -
- Memory -
- -
-
-
- - - Instruction... - - - - - - - -
-
-
- - A - -
-
-
- - - A - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - -
-
-
- - INSTR - -
-
-
- - - INSTR - - - - - - - -
-
-
- MEM_SIZE -
-
-
- - - MEM_SIZE - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - -
-
-
- - instr_addr - -
-
-
- - - instr_addr - - - - - - - -
-
-
- - instr - -
-
-
- - - instr - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - -
-
-
- - — входные сигналы - -
-
-
- - - — входные сигналы - - - - - - - -
-
-
- MEM_WE -
-
-
- - - MEM_WE - - - - - - - -
-
-
- MEM_REQ -
-
-
- - - MEM_REQ - - - - - - - -
-
-
- MEM_WD -
-
-
- - - MEM_WD - - - - - - - -
-
-
- MEM_ADDR -
-
-
- - - MEM_ADDR - - - - - - - -
-
-
- INSTR_ADDR -
-
-
- - - INSTR_ADDR - - - - - - - -
-
-
- не подключён -
-
-
- - - не подключён - - - - - - - - -
-
-
- 3 -
-
-
- - - 3 - - - - - - - -
-
-
- STALL -
-
-
- - - STALL - - - - - - - - - -
-
-
- stall -
-
-
- - - stall - - - - - - - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - - - -
-
-
- - Data -
- Memory -
- -
-
-
- - - Data... - - - - - - - -
-
-
- - ADDR - -
-
-
- - - ADDR - - - - - - - -
-
-
- - WE - -
-
-
- - - WE - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- REQ -
-
-
- - - REQ - - - - - - - -
-
-
- - WD - -
-
-
- - - WD - - - - - - - -
-
-
- BE -
-
-
- - - BE - - - - - - - -
-
-
- READY -
-
-
- - - READY - - - - - - - -
-
-
- не подключён -
-
-
- - - не подключён - - - - - - - -
-
-
- 4'b1111 -
-
-
- - - 4'b1111 - - - - - - - - - -
-
-
- 4 -
-
-
- - - 4 - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
Core

Core...
RST
RST
MEM_RD
MEM_RD
clk_i
clk_i
Instruction
Memory
Instruction...
A
A
RD
RD
INSTR
INSTR
MEM_SIZE
MEM_SIZE

rst_i

rst_i
instr_addr
instr_addr
instr
instr
clk_i
clk_i

rst_i

rst_i
—  input signals
—  input signals
MEM_WE
MEM_WE
MEM_REQ
MEM_REQ
MEM_WD
MEM_WD
MEM_ADDR
MEM_ADDR
INSTR_ADDR
INSTR_ADDR
not connected
not connected
3
3
STALL
STALL
stall
stall
clk_i
clk_i
32
32
32
32

rst_i

rst_i
Data
Memory
Data...
ADDR
ADDR
WE
WE
RD
RD
clk_i
clk_i
REQ
REQ
WD
WD
BE
BE
READY
READY
not connected
not connected
4'b1111
4'b1111
4
4
32
32
32
32Text is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_07_dp/fig_02.excel.png b/.pic/Labs/lab_07_dp/fig_02.excel.png index f2bc681..9bd9baf 100644 Binary files a/.pic/Labs/lab_07_dp/fig_02.excel.png and b/.pic/Labs/lab_07_dp/fig_02.excel.png differ diff --git a/.pic/Labs/lab_07_dp/fig_02.xlsx b/.pic/Labs/lab_07_dp/fig_02.xlsx index 80a4043..21ae861 100644 Binary files a/.pic/Labs/lab_07_dp/fig_02.xlsx and b/.pic/Labs/lab_07_dp/fig_02.xlsx differ diff --git a/.pic/Labs/lab_08_lsu/fig_01.drawio.svg b/.pic/Labs/lab_08_lsu/fig_01.drawio.svg index de371a3..3147bd8 100644 --- a/.pic/Labs/lab_08_lsu/fig_01.drawio.svg +++ b/.pic/Labs/lab_08_lsu/fig_01.drawio.svg @@ -1,1134 +1,4 @@ - - - - - - - -
-
-
- LOAD / -
- STORE -
- UNIT -
-
-
- - - LOAD /... - - - - - - - -
-
-
- - Core -
-
- -
-
-
- - - Core... - - - - - - - -
-
-
- - RST - -
-
-
- - - RST - - - - - - - -
-
-
- MEM_RD -
-
-
- - - MEM_RD - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - - - -
-
-
- - Instruction -
- Memory -
- -
-
-
- - - Instruction... - - - - - - - -
-
-
- - ADDR - -
-
-
- - - ADDR - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - -
-
-
-

-
-

-
-
-
- - - - - - - - -
-
-
- - INSTR - -
-
-
- - - INSTR - - - - - - - -
-
-
- MEM_SIZE -
-
-
- - - MEM_SIZE - - - - - - - -
-
-
- - instr_addr - -
-
-
- - - instr_addr - - - - - - - -
-
-
- - instr - -
-
-
- - - instr - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - -
-
-
- - — входные сигналы - -
-
-
- - - — входные сигналы - - - - - - - -
-
-
- MEM_WE -
-
-
- - - MEM_WE - - - - - - - -
-
-
- MEM_REQ -
-
-
- - - MEM_REQ - - - - - - - -
-
-
- MEM_WD -
-
-
- - - MEM_WD - - - - - - - -
-
-
- MEM_ADDR -
-
-
- - - MEM_ADDR - - - - - - - -
-
-
- INST_ADDR -
-
-
- - - INST_ADDR - - - - - - - - -
-
-
- 3 -
-
-
- - - 3 - - - - - - - -
-
-
- STALL -
-
-
- - - STALL - - - - - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- - Data -
- Memory -
- -
-
-
- - - Data... - - - - - - - -
-
-
- - A - -
-
-
- - - A - - - - - - - -
-
-
- - WE - -
-
-
- - - WE - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- REQ -
-
-
- - - REQ - - - - - - - -
-
-
- - WD - -
-
-
- - - WD - - - - - - - -
-
-
- CORE_REQ -
-
-
- - - CORE_REQ - - - - - - - -
-
-
- CORE_WE -
-
-
- - - CORE_WE - - - - - - - -
-
-
- CORE_WD -
-
-
- - - CORE_WD - - - - - - - - -
-
-
- STALL -
-
-
- - - STALL - - - - - - - -
-
-
- CORE_RD -
-
-
- - - CORE_RD - - - - - - - -
-
-
- BE -
-
-
- - - BE - - - - - - - -
-
-
- MEM_WD -
-
-
- - - MEM_WD - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- MEM_BE -
-
-
- - - MEM_BE - - - - - - - -
-
-
- MEM_WE -
-
-
- - - MEM_WE - - - - - - - -
-
-
- MEM_REQ -
-
-
- - - MEM_REQ - - - - - - - -
-
-
- READY -
-
-
- - - READY - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- MEM_ADDR -
-
-
- - - MEM_ADDR - - - - - - - - - - - - -
-
-
- MEM_RD -
-
-
- - - MEM_RD - - - - - - - - -
-
-
- READY -
-
-
- - - READY - - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - - - -
-
-
- 4 -
-
-
- - - 4 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - -
-
-
- - RST - -
-
-
- - - RST - - - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - - -
-
-
- - 32 -
- -
-
-
- - - 32 - - - - - - - - -
-
-
- - 32 -
- -
-
-
- - - 32 - - - - - - - - - -
-
-
- CORE_SIZE -
-
-
- - - CORE_SIZE - - - - - - - -
-
-
- CORE_ADDR -
-
-
- - - CORE_ADDR - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
LOAD /
STORE
UNIT
LOAD /...
Core

Core...
RST
RST
MEM_RD
MEM_RD
clk_i
clk_i
Instruction
Memory
Instruction...
ADDR
ADDR
RD
RD


INSTR
INSTR
MEM_SIZE
MEM_SIZE
instr_addr
instr_addr
instr
instr
clk_i
clk_i

rst_i

rst_i
— input signals
— input signals
MEM_WE
MEM_WE
MEM_REQ
MEM_REQ
MEM_WD
MEM_WD
MEM_ADDR
MEM_ADDR
INST_ADDR
INST_ADDR
3
3
STALL
STALL
32
32
32
32
Data
Memory
Data...
A
A
WE
WE
RD
RD
clk_i
clk_i
REQ
REQ
WD
WD
CORE_REQ
CORE_REQ
CORE_WE
CORE_WE
CORE_WD
CORE_WD
STALL
STALL
CORE_RD
CORE_RD
BE
BE
MEM_WD
MEM_WD
32
32
MEM_BE
MEM_BE
MEM_WE
MEM_WE
MEM_REQ
MEM_REQ
READY
READY
clk_i
clk_i
MEM_ADDR
MEM_ADDR
MEM_RD
MEM_RD
READY
READY

rst_i

rst_i
4
4
32
32
32
32
32
32
RST
RST

rst_i

rst_i
32
32
32
32
CORE_SIZE
CORE_SIZE
CORE_ADDR
CORE_ADDRText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_08_lsu/fig_06.drawio.svg b/.pic/Labs/lab_08_lsu/fig_06.drawio.svg index 184d1f0..d750dda 100644 --- a/.pic/Labs/lab_08_lsu/fig_06.drawio.svg +++ b/.pic/Labs/lab_08_lsu/fig_06.drawio.svg @@ -1,1451 +1,4 @@ - - - - - - - - - - - - -
-
-
- core_req_i -
-
-
- - - core_req_i - - - - - - - - -
-
-
- core_we_i -
-
-
- - - core_we_i - - - - - - - -
-
-
- core_size_i -
-
-
- - - core_size_i - - - - - - - -
-
-
- core_wd_i -
-
-
- - - core_wd_i - - - - - - - -
-
-
- core_addr_i -
-
-
- - - core_addr_i - - - - - - - -
-
-
- core_rd_o -
-
-
- - - core_rd_o - - - - - - - -
-
-
- mem_rd_i -
-
-
- - - mem_rd_i - - - - - - - - - - - -
-
-
- mem_rd_i[7:0] -
-
-
- - - mem_rd_i[7:0] - - - - - - - -
-
-
- mem_rd_i[15:8] -
-
-
- - - mem_rd_i[15:8] - - - - - - - -
-
-
- mem_rd_i[23:16] -
-
-
- - - mem_rd_i[23:16] - - - - - - - -
-
-
- mem_rd_i[31:24] -
-
-
- - - mem_rd_i[31:24] - - - - - - - - - - - - - - - - -
-
-
- SE -
-
-
- - - SE - - - - - - - - - - -
-
-
- SE -
-
-
- - - SE - - - - - - - - - - -
-
-
- SE -
-
-
- - - SE - - - - - - - - - - -
-
-
- SE -
-
-
- - - SE - - - - - - - - - - - - - - - - - - - - - -
-
-
- ZE -
-
-
- - - ZE - - - - - - - - - - -
-
-
- ZE -
-
-
- - - ZE - - - - - - - - - - -
-
-
- ZE -
-
-
- - - ZE - - - - - - - - - - -
-
-
- ZE -
-
-
- - - ZE - - - - - - - - - - - - - - - - - - - - - - - -
-
-
- SE -
-
-
- - - SE - - - - - - - - - - -
-
-
- SE -
-
-
- - - SE - - - - - - - - - - - - - - -
-
-
- ZE -
-
-
- - - ZE - - - - - - - - - - -
-
-
- ZE -
-
-
- - - ZE - - - - - - - - - - - - -
-
-
- mem_rd_i[15:0] -
-
-
- - - mem_rd_i[15:0] - - - - - - -
-
-
- mem_rd_i[31:16] -
-
-
- - - mem_rd_i[31:16] - - - - - - - - - - - - - - - -
-
-
- half_offset -
-
-
- - - half_offset - - - - - - - - - - - -
-
-
- half_offset -
-
-
- - - half_offset - - - - - - - - -
-
-
- 2'b00 -
-
-
- - - 2'b00 - - - - - - -
-
-
- 2'b01 -
-
-
- - - 2'b01 - - - - - - -
-
-
- 2'b10 -
-
-
- - - 2'b10 - - - - - - -
-
-
- 2'b11 -
-
-
- - - 2'b11 - - - - - - -
-
-
- 2'b00 -
-
-
- - - 2'b00 - - - - - - -
-
-
- 2'b01 -
-
-
- - - 2'b01 - - - - - - -
-
-
- 2'b10 -
-
-
- - - 2'b10 - - - - - - -
-
-
- 2'b11 -
-
-
- - - 2'b11 - - - - - - -
-
-
- 1'b0 -
-
-
- - - 1'b0 - - - - - - -
-
-
- 1'b1 -
-
-
- - - 1'b1 - - - - - - -
-
-
- 1'b0 -
-
-
- - - 1'b0 - - - - - - -
-
-
- 1'b1 -
-
-
- - - 1'b1 - - - - - - - - -
-
-
- LDST_W -
-
-
- - - LDST_W - - - - - - -
-
-
- LDST_B -
-
-
- - - LDST_B - - - - - - -
-
-
- LDST_BU -
-
-
- - - LDST_BU - - - - - - -
-
-
- LDST_H -
-
-
- - - LDST_H - - - - - - -
-
-
- LDST_HU -
-
-
- - - LDST_HU - - - - - - - - - -
-
-
- LDST_H -
-
-
- - - LDST_H - - - - - - -
-
-
- LDST_W -
-
-
- - - LDST_W - - - - - - -
-
-
- LDST_B -
-
-
- - - LDST_B - - - - - - - - - - - -
-
-
- << -
-
-
- - - << - - - - - - - -
-
-
- 4'b0001 -
-
-
- - - 4'b0001 - - - - - - -
-
-
- 4'b1111 -
-
-
- - - 4'b1111 - - - - - - - -
-
-
- 4'b0011 -
-
-
- - - 4'b0011 - - - - - - - -
-
-
- 4'b1100 -
-
-
- - - 4'b1100 - - - - - - - - - - - - - -
-
-
- byte_offset -
-
-
- - - byte_offset - - - - - - -
-
-
- 0 -
-
-
- - - 0 - - - - - - -
-
-
- 1 -
-
-
- - - 1 - - - - - - -
-
-
- byte_offset -
-
-
- - - byte_offset - - - - - - - - -
-
-
- LDST_W -
-
-
- - - LDST_W - - - - - - -
-
-
- LDST_H -
-
-
- - - LDST_H - - - - - - -
-
-
- LDST_B -
-
-
- - - LDST_B - - - - - - - - - - - -
-
-
- {{2{core_wd_i[15:0]}}} -
-
-
- - - {{2{core_wd_i[15:0]}}} - - - - - - -
-
-
- {{4{core_wd_i[7:0]}}} -
-
-
- - - {{4{core_wd_i[7:0]}}} - - - - - - -
-
-
- core_wd_i -
-
-
- - - core_wd_i - - - - - - - - - - - - - - - - - - -
-
-
- stall -
-
-
- - - stall - - - - - - - -
-
-
-

- - clk_i - -

-
-
-
- - - clk_i - - - - - - - - - -
-
-
-

- - rst_i - -

-
-
-
- - - rst_i - - - - - - - - -
-
-
- mem_ready_i -
-
-
- - - mem_ready_i - - - - - - - - - - -
-
-
- mem_we_o -
-
-
- - - mem_we_o - - - - - - -
-
-
- mem_req_o -
-
-
- - - mem_req_o - - - - - - -
-
-
- core_stall_o -
-
-
- - - core_stall_o - - - - - - -
-
-
- mem_wd_o -
-
-
- - - mem_wd_o - - - - - - -
-
-
- mem_addr_o -
-
-
- - - mem_addr_o - - - - - - -
-
-
- mem_be_o -
-
-
- - - mem_be_o - - - - - - -
-
-
- byte_offset = core_addr_i[1:0] -
-
-
- - - byte_offset = core_addr_i[1... - - - - - - -
-
-
- half_offset = core_addr_i[1] -
-
-
- - - half_offset = core_addr_i[... - - - - - - - - - - -
-
-
- SE -
-
-
- - - SE - - - - - - -
-
-
- — знаковое расширение -
-
-
- - - — знаковое расширение - - - - - - - - - - -
-
-
- ZE -
-
-
- - - ZE - - - - - - -
-
-
- — расширение нулями -
-
-
- - - — расширение нулями - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
core_req_i
core_req_i
core_we_i
core_we_i
core_size_i
core_size_i
core_wd_i
core_wd_i
core_addr_i
core_addr_i
core_rd_o
core_rd_o
mem_rd_i
mem_rd_i
mem_rd_i[7:0]
mem_rd_i[7:0]
mem_rd_i[15:8]
mem_rd_i[15:8]
mem_rd_i[23:16]
mem_rd_i[23:16]
mem_rd_i[31:24]
mem_rd_i[31:24]
SE
SE
SE
SE
SE
SE
SE
SE
ZE
ZE
ZE
ZE
ZE
ZE
ZE
ZE
SE
SE
SE
SE
ZE
ZE
ZE
ZE
mem_rd_i[15:0]
mem_rd_i[15:0]
mem_rd_i[31:16]
mem_rd_i[31:16]
half_offset
half_offset
half_offset
half_offset
2'b00
2'b00
2'b01
2'b01
2'b10
2'b10
2'b11
2'b11
2'b00
2'b00
2'b01
2'b01
2'b10
2'b10
2'b11
2'b11
1'b0
1'b0
1'b1
1'b1
1'b0
1'b0
1'b1
1'b1
LDST_W
LDST_W
LDST_B
LDST_B
LDST_BU
LDST_BU
LDST_H
LDST_H
LDST_HU
LDST_HU
LDST_H
LDST_H
LDST_W
LDST_W
LDST_B
LDST_B
<<
<<
4'b0001
4'b0001
4'b1111
4'b1111
4'b0011
4'b0011
4'b1100
4'b1100
byte_offset
byte_offset
0
0
1
1
byte_offset
byte_offset
LDST_W
LDST_W
LDST_H
LDST_H
LDST_B
LDST_B
{{2{core_wd_i[15:0]}}}
{{2{core_wd_i[15:0]}}}
{{4{core_wd_i[7:0]}}}
{{4{core_wd_i[7:0]}}}
core_wd_i
core_wd_i
stall
stall

clk_i

clk_i

rst_i

rst_i
mem_ready_i
mem_ready_i
mem_we_o
mem_we_o
mem_req_o
mem_req_o
core_stall_o
core_stall_o
mem_wd_o
mem_wd_o
mem_addr_o
mem_addr_o
mem_be_o
mem_be_o
byte_offset = core_addr_i[1:0]
byte_offset = core_addr_i[1...
half_offset = core_addr_i[1]
half_offset = core_addr_i[...
SE
SE
— sign extension
— sign extension
ZE
ZE
— zero extension
— zero extensionText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_10_irq/fig_03.drawio.svg b/.pic/Labs/lab_10_irq/fig_03.drawio.svg index 9e6e473..37739ab 100644 --- a/.pic/Labs/lab_10_irq/fig_03.drawio.svg +++ b/.pic/Labs/lab_10_irq/fig_03.drawio.svg @@ -1,4 +1,4 @@ -

Main
Decoder

flag

Register
File
imm_S
imm_U
4
0
RD1
RD2
gpr_we
WE

clk_i

wb_sel
 mem_size
mem_we
alu_op
b_sel
a_sel
jal
b
instr
RA1
RA2
WA
WD
[19:15]
[24:20]
[11:07]
[31:20]
[31:12], 12'h000
[31:25][11:7]
[31][19:12][20][30:21],1'b0
[31][7][30:25][11:8],1'b0
imm_J
imm_B
4
PC

clk_i

rst_i

jalr
ALU
SE
SE
+
mem_wd_o
instr_i
mem_addr_o
instr_addr_o
mem_rd_i
mem_we_o
mem_size_o
instr_addr_o

instr_i

mem_addr_o

mem_we_o

mem_size_o

rst_i

clk_i

SE

0

1

0

1

flag

32
/

32
/

32
/

32
/

32
/

12
/

12
/

21
/

13
/

32
/

mret
SE
mem_req 

mem_req_o

imm_I

— входные сигналы
— выходные сигналы
mem_req_o

imm_I

RD1

flag

— провода, разорванные        для удобства                    отображения схемы
PC

0
1
2
3
4

0
1
2

32
stall_i
stall_i

32
/

2
3
3
5
mem_wd_o
mem_rd_i
wb_data
wb_data
wb_data
32
PC
2
0
2
1
csr_wd
 illegal_instr
CONTROL
STATUS
REGISTERS
WE

clk_i

addr
pc
mcause
rs1_data
rst
imm_data
trap
opcode
read_data
mie
mepc
mtvec
csr_we
csr_op
3
irq
trap
rst_i
csr_wd
mie
RD1
PC
[19:15]
ZE

5
/

32
/

imm_Z

imm_Z

instr_i[31:20]

mret
IRQ
CONTROLLER
exception_i

clk_i

irq_req_i
mie_i
rst_i
irq_cause_o
irq_ret_o
rst_i
trap
mret
irq
irq_ret_o
irq_req_i
mie[16]

imm_Z

csr_wd
irq
trap
mret
mie
irq_req_i
irq_ret_o
jalr
PC
jalr
32
32
32
32
12
32
32
32
32

1

0

stall_i
trap
trap
trap
ill_instr

0

1

ill_instr
32
32
irq
ill_instr
ill_instr
mret_i
irq_o
32'h0000_0002

imm_I

+
RD1
jalr
{[31:1],1'b0}

1

0

1

0

trap
trap
en
rst
 \ No newline at end of file +

Main
Decoder

Main...

flag

flag
Register
File
Register...
imm_S
imm_S
imm_U
imm_U
4
4
0
0
RD1
RD1
RD2
RD2
gpr_we
gpr_we
WE
WE

clk_i

clk_i
wb_sel
wb_sel
 mem_size
 mem_size
mem_we
mem_we
alu_op
alu_op
b_sel
b_sel
a_sel
a_sel
jal
jal
b
b
instr
instr
RA1
RA1
RA2
RA2
WA
WA
WD
WD
[19:15]
[19:15]
[24:20]
[24:20]
[11:07]
[11:07]
[31:20]
[31:20]
[31:12], 12'h000
[31:12], 12'h000
[31:25][11:7]
[31:25][11:7]
[31][19:12][20][30:21],1'b0
[31][19:12][20][30:21],1'b0
[31][7][30:25][11:8],1'b0
[31][7][30:25][11:8],1'b0
imm_J
imm_J
imm_B
imm_B
4
4
PC
PC

clk_i

clk_i

rst_i

rst_i
jalr
jalr
ALU
ALU
SE
SE
SE
SE
+
+
mem_wd_o
mem_wd_o
instr_i
instr_i
mem_addr_o
mem_addr_o
instr_addr_o
instr_addr_o
mem_rd_i
mem_rd_i
mem_we_o
mem_we_o
mem_size_o
mem_size_o
instr_addr_o
instr_addr_o

instr_i

instr_i

mem_addr_o

mem_addr_o
mem_we_o
mem_we_o

mem_size_o

mem_size_o

rst_i

rst_i

clk_i

clk_i
SE
SE

0

1

0...

0

1

0...

flag

flag

32
/

32...

32
/

32...

32
/

32...

32
/

32...

32
/

32...

12
/

12...

12
/

12...

21
/

21...

13
/

13...

32
/

32...
mret
mret
SE
SE
mem_req 
mem_req 

mem_req_o

mem_req_o

imm_I

imm_I
— input signals
— input signals
— output signals
— output signals
mem_req_o
mem_req_o

imm_I

imm_I
RD1
RD1

flag

flag
— wires broken for                    readability
— wires broken for...
PC
PC

0
1
2
3
4

0...

0
1
2

0...
32
32
stall_i
stall_i
stall_i
stall_i

32
/

32...
2
2
3
3
3
3
5
5
mem_wd_o
mem_wd_o
mem_rd_i
mem_rd_i
wb_data
wb_data
wb_data
wb_data
wb_data
wb_data
32
32
PC
PC
2
2
0
0
2
2
1
1
csr_wd
csr_wd
 illegal_instr
 illegal_instr
CONTROL
STATUS
REGISTERS
CONTROL...
WE
WE

clk_i

clk_i
addr
addr
pc
pc
mcause
mcause
rs1_data
rs1_data
rst
rst
imm_data
imm_data
trap
trap
opcode
opcode
read_data
read_data
mie
mie
mepc
mepc
mtvec
mtvec
csr_we
csr_we
csr_op
csr_op
3
3
irq
irq
trap
trap
rst_i
rst_i
csr_wd
csr_wd
mie
mie
RD1
RD1
PC
PC
[19:15]
[19:15]
ZE
ZE

5
/

5...

32
/

32...

imm_Z

imm_Z

imm_Z

imm_Z

instr_i[31:20]

instr_i[31:20]
mret
mret
IRQ
CONTROLLER
IRQ...
exception_i
exception_i

clk_i

clk_i
irq_req_i
irq...
mie_i
mie_i
rst_i
rst_i
irq_cause_o
irq_cause...
irq_ret_o
irq_ret_o
rst_i
rst_i
trap
trap
mret
mret
irq
irq
irq_ret_o
irq_ret_o
irq_req_i
irq_req_i
mie[16]
mie[16]

imm_Z

imm_Z
csr_wd
csr_wd
irq
irq
trap
trap
mret
mret
mie
mie
irq_req_i
irq_req_i
irq_ret_o
irq_ret_o
jalr
jalr
PC
PC
jalr
jalr
32
32
32
32
32
32
32
32
12
12
32
32
32
32
32
32
32
32

1

0

1...
stall_i
stall_i
trap
trap
trap
trap
trap
trap
ill_instr
ill_ins...

0

1

0...
ill_instr
ill_ins...
32
32
32
32
irq
irq
ill_instr
ill_ins...
ill_instr
ill_ins...
mret_i
mret_i
irq_o
irq_o
32'h0000_0002
32'h0000_0002

imm_I

imm_I
+
+
RD1
RD1
jalr
jalr
{[31:1],1'b0}
{[31:1],1'b0}

1

0

1...

1

0

1...
trap
trap
trap
trap
en
en
rst
rstText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_11_irq_integration/fig_01.drawio.svg b/.pic/Labs/lab_11_irq_integration/fig_01.drawio.svg index 46ba67c..d4dec36 100644 --- a/.pic/Labs/lab_11_irq_integration/fig_01.drawio.svg +++ b/.pic/Labs/lab_11_irq_integration/fig_01.drawio.svg @@ -1,4 +1,4 @@ -

Main
Decoder

flag

Register
File
imm_S
imm_U
4
0
RD1
RD2
gpr_we
WE

clk_i

wb_sel
 mem_size
mem_we
alu_op
b_sel
a_sel
jal
b
instr
RA1
RA2
WA
WD
[19:15]
[24:20]
[11:07]
[31:20]
[31:12], 12'h000
[31:25][11:7]
[31][19:12][20][30:21],1'b0
[31][7][30:25][11:8],1'b0
imm_J
imm_B
4
PC

clk_i

rst_i

jalr
ALU
SE
SE
+
mem_wd_o
instr_i
mem_addr_o
instr_addr_o
mem_rd_i
mem_we_o
mem_size_o
instr_addr_o

instr_i

mem_addr_o

mem_we_o

mem_size_o

rst_i

clk_i

SE

0

1

0

1

flag

32
/

32
/

32
/

32
/

32
/

12
/

12
/

21
/

13
/

32
/

mret
SE
mem_req 

mem_req_o

imm_I

— входные сигналы
— выходные сигналы
mem_req_o

imm_I

RD1

flag

— провода, разорванные        для удобства                    отображения схемы
PC

0
1
2
3
4

0
1
2

32
stall_i
stall_i

32
/

2
3
3
5
mem_wd_o
mem_rd_i
wb_data
wb_data
wb_data
32
PC
2
0
2
1
csr_wd
 illegal_instr
CONTROL
STATUS
REGISTERS
WE

clk_i

addr
pc
mcause
rs1_data
rst
imm_data
trap
opcode
read_data
mie
mepc
mtvec
csr_we
csr_op
3
irq
trap
rst_i
csr_wd
mie
RD1
PC
[19:15]
ZE

5
/

32
/

imm_Z

imm_Z

instr_i[31:20]

mret
IRQ
CONTROLLER
exception_i

clk_i

irq_req_i
mie_i
rst_i
irq_cause_o
irq_ret_o
rst_i
trap
mret
irq
irq_ret_o
irq_req_i
mie[16]

imm_Z

csr_wd
irq
trap
mret
mie
irq_req_i
irq_ret_o
jalr
PC
jalr
32
32
32
32
12
32
32
32
32

1

0

stall_i
trap
trap
trap
ill_instr

0

1

ill_instr
32
32
irq
ill_instr
ill_instr
mret_i
irq_o
32'h0000_0002

imm_I

+
RD1
jalr
{[31:1],1'b0}

1

0

1

0

trap
trap
en
rst
 \ No newline at end of file +

Main
Decoder

Main...

flag

flag
Register
File
Register...
imm_S
imm_S
imm_U
imm_U
4
4
0
0
RD1
RD1
RD2
RD2
gpr_we
gpr_we
WE
WE

clk_i

clk_i
wb_sel
wb_sel
 mem_size
 mem_size
mem_we
mem_we
alu_op
alu_op
b_sel
b_sel
a_sel
a_sel
jal
jal
b
b
instr
instr
RA1
RA1
RA2
RA2
WA
WA
WD
WD
[19:15]
[19:15]
[24:20]
[24:20]
[11:07]
[11:07]
[31:20]
[31:20]
[31:12], 12'h000
[31:12], 12'h000
[31:25][11:7]
[31:25][11:7]
[31][19:12][20][30:21],1'b0
[31][19:12][20][30:21],1'b0
[31][7][30:25][11:8],1'b0
[31][7][30:25][11:8],1'b0
imm_J
imm_J
imm_B
imm_B
4
4
PC
PC

clk_i

clk_i

rst_i

rst_i
jalr
jalr
ALU
ALU
SE
SE
SE
SE
+
+
mem_wd_o
mem_wd_o
instr_i
instr_i
mem_addr_o
mem_addr_o
instr_addr_o
instr_addr_o
mem_rd_i
mem_rd_i
mem_we_o
mem_we_o
mem_size_o
mem_size_o
instr_addr_o
instr_addr_o

instr_i

instr_i

mem_addr_o

mem_addr_o
mem_we_o
mem_we_o

mem_size_o

mem_size_o

rst_i

rst_i

clk_i

clk_i
SE
SE

0

1

0...

0

1

0...

flag

flag

32
/

32...

32
/

32...

32
/

32...

32
/

32...

32
/

32...

12
/

12...

12
/

12...

21
/

21...

13
/

13...

32
/

32...
mret
mret
SE
SE
mem_req 
mem_req 

mem_req_o

mem_req_o

imm_I

imm_I
— input signals
— input signals
— output signals

— output signals
mem_req_o
mem_req_o

imm_I

imm_I
RD1
RD1

flag

flag
— wires broken for                    readability
— wires broken for...
PC
PC

0
1
2
3
4

0...

0
1
2

0...
32
32
stall_i
stall_i
stall_i
stall_i

32
/

32...
2
2
3
3
3
3
5
5
mem_wd_o
mem_wd_o
mem_rd_i
mem_rd_i
wb_data
wb_data
wb_data
wb_data
wb_data
wb_data
32
32
PC
PC
2
2
0
0
2
2
1
1
csr_wd
csr_wd
 illegal_instr
 illegal_instr
CONTROL
STATUS
REGISTERS
CONTROL...
WE
WE

clk_i

clk_i
addr
addr
pc
pc
mcause
mcause
rs1_data
rs1_data
rst
rst
imm_data
imm_data
trap
trap
opcode
opcode
read_data
read_data
mie
mie
mepc
mepc
mtvec
mtvec
csr_we
csr_we
csr_op
csr_op
3
3
irq
irq
trap
trap
rst_i
rst_i
csr_wd
csr_wd
mie
mie
RD1
RD1
PC
PC
[19:15]
[19:15]
ZE
ZE

5
/

5...

32
/

32...

imm_Z

imm_Z

imm_Z

imm_Z

instr_i[31:20]

instr_i[31:20]
mret
mret
IRQ
CONTROLLER
IRQ...
exception_i
exception_i

clk_i

clk_i
irq_req_i
irq...
mie_i
mie_i
rst_i
rst_i
irq_cause_o
irq_cause...
irq_ret_o
irq_ret_o
rst_i
rst_i
trap
trap
mret
mret
irq
irq
irq_ret_o
irq_ret_o
irq_req_i
irq_req_i
mie[16]
mie[16]

imm_Z

imm_Z
csr_wd
csr_wd
irq
irq
trap
trap
mret
mret
mie
mie
irq_req_i
irq_req_i
irq_ret_o
irq_ret_o
jalr
jalr
PC
PC
jalr
jalr
32
32
32
32
32
32
32
32
12
12
32
32
32
32
32
32
32
32

1

0

1...
stall_i
stall_i
trap
trap
trap
trap
trap
trap
ill_instr
ill_ins...

0

1

0...
ill_instr
ill_ins...
32
32
32
32
irq
irq
ill_instr
ill_ins...
ill_instr
ill_ins...
mret_i
mret_i
irq_o
irq_o
32'h0000_0002
32'h0000_0002

imm_I

imm_I
+
+
RD1
RD1
jalr
jalr
{[31:1],1'b0}
{[31:1],1'b0}

1

0

1...

1

0

1...
trap
trap
trap
trap
en
en
rst
rstText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_12_daisy_chain/fig_01.png b/.pic/Labs/lab_12_daisy_chain/fig_01.png index 442c67b..c2f23a1 100644 Binary files a/.pic/Labs/lab_12_daisy_chain/fig_01.png and b/.pic/Labs/lab_12_daisy_chain/fig_01.png differ diff --git a/.pic/Labs/lab_12_daisy_chain/fig_02.drawio.svg b/.pic/Labs/lab_12_daisy_chain/fig_02.drawio.svg index c25dc11..f05e033 100644 --- a/.pic/Labs/lab_12_daisy_chain/fig_02.drawio.svg +++ b/.pic/Labs/lab_12_daisy_chain/fig_02.drawio.svg @@ -1,866 +1,4 @@ - - - - - - - - -
-
-
- - - ready_i - - -
-
-
- - - ready_i - - - - - - - -
-
-
- - irq_o - -
-
-
- - - irq_o - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-
-
- ... -
-
-
- - - ... - - - - - - - - - - - - - - - - - -
-
-
- cause[15] -
-
-
- - - cause[15] - - - - - - - - - -
-
-
- cause[1] -
-
-
- - - cause[1] - - - - - - - -
-
-
- cause[0] -
-
-
- - - cause[0] - - - - - - - -
-
-
- masked_irq_i[0] -
-
-
- - - masked_irq_i[0] - - - - - - - -
-
-
- masked_irq_i[1] -
-
-
- - - masked_irq_i[1] - - - - - - - -
-
-
- masked_irq_i[15] -
-
-
- - - masked_irq_i[15] - - - - - - - - - - - - - -
-
-
- - - 16 -
- - -
-
-
- - - 16 - - - - - - - - - -
-
-
- - - 16 -
- - -
-
-
- - - 16 - - - - - - - - - - -
-
-
- - - 32 -
- - -
-
-
- - - 32 - - - - - - - - - - -
-
-
- — побитовая свёртка по ИЛИ -
-
-
- - - — побитовая свёртка по ИЛИ - - - - - - - -
-
-
- masked_irq_i -
-
-
- - - masked_irq_i - - - - - - - -
-
-
- - - ready - - - _i - - -
-
-
- - - ready_i - - - - - - - -
-
-
- - irq_ret_i - -
-
-
- - - irq_ret_i - - - - - - - -
-
-
-

- - clk_i - -

-
-
-
- - - clk_i - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst_i - - - - - - - -
-
-
- masked_irq_i -
-
-
- - - masked_irq_i - - - - - - - - -
-
-
- — входные сигналы -
-
-
- - - — входные сигналы - - - - - - - -
-
-
- irq_ret_o -
-
-
- - - irq_ret_o - - - - - - - -
-
-
- - irq_cause_o - -
-
-
- - - irq_cause_o - - - - - - - -
-
-
- - irq_o - -
-
-
- - - irq_o - - - - - - - - -
-
-
- — выходные сигналы -
-
-
- - - — выходные сигналы - - - - - - - - - - - -
-
-
-

- - clk_i - -

-
-
-
- - - clk_i - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst_i - - - - - - - - - -
-
-
- en -
-
-
- - - en - - - - - - - - -
-
-
- cause -
-
-
- - - cause - - - - - - - -
-
-
- - - 16 -
- - -
-
-
- - - 16 - - - - - - - - - - - -
-
-
- 1 -
-
-
- - - 1 - - - - - - -
-
-
- 0 -
-
-
- - - 0 - - - - - - - - -
-
-
- 16'd0 -
-
-
- - - 16'd0 - - - - - - - - -
-
-
- - irq_ret_i - -
-
-
- - - irq_ret_i - - - - - - - - -
-
-
- irq_ret_o -
-
-
- - - irq_ret_o - - - - - - - -
-
-
- - - 16 -
- - -
-
-
- - - 16 - - - - - - - - -
-
-
- - - 16 -
- - -
-
-
- - - 16 - - - - - - - - - -
-
-
- irq_cause_o -
-
-
- - - irq_cause_o - - - - - - -
-
-
- {12'h800,cause,4'h0} -
-
-
- - - {12'h800,cause,4'h0} - - - - - - - -
-
-
- - - 32 -
- - -
-
-
- - - 32 - - - - - - - - -
-
-
- cause -
-
-
- - - cause - - - - - - -
-
-
- — внутренний сигнал -
-
-
- - - — внутренний сигнал - - - - - - - -
-
-
- - irq_o - -
-
-
- - - irq_o - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
ready_i
ready_i
irq_o
irq_o
...
...
cause[15]
cause[15]
cause[1]
cause[1]
cause[0]
cause[0]
masked_irq_i[0]
masked_irq_i[0]
masked_irq_i[1]
masked_irq_i[1]
masked_irq_i[15]
masked_irq_i[15]
16
16
16
16
32
32
— bitwise OR reduction
— bitwise OR reduction
masked_irq_i
masked_irq_i
ready_i
ready_i
irq_ret_i
irq_ret_i

clk_i

clk_i
rst_i
rst_i
masked_irq_i
masked_irq_i
— input signals
— input signals
irq_ret_o
irq_ret_o
irq_cause_o
irq_cause_o
irq_o
irq_o
— output signals
— output signals

clk_i

clk_i
rst_i
rst_i
en
en
cause
cause
16
16
1
1
0
0
16'd0
16'd0
irq_ret_i
irq_ret_i
irq_ret_o
irq_ret_o
16
16
16
16
irq_cause_o
irq_cause_o
{12'h800,cause,4'h0}
{12'h800,cause,4'h0}
32
32
cause
cause
— internal signal
— internal signal
irq_o
irq_oText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_13_periph/fig_01.drawio.svg b/.pic/Labs/lab_13_periph/fig_01.drawio.svg index 8f6da97..4261c03 100644 --- a/.pic/Labs/lab_13_periph/fig_01.drawio.svg +++ b/.pic/Labs/lab_13_periph/fig_01.drawio.svg @@ -1,2006 +1,4 @@ - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - -
-
-
- - входные сигналы - -
-
-
- - - входные сигналы - - - - - - - - - - - -
-
-
- 255 -
-
-
- - - 255 - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - -
-
-
-
- - внутренний сигнал, оборванный для улучшения читаемости схемы - -
-
-
-
-
- - - внутренний сигнал, оборванный для улучшения читаемости схемы - - - - - - - -
-
-
- — -
-
-
- - - — - - - - - - - -
-
-
- LOAD/ -
- STORE -
- UNIT -
-
-
- - - LOAD/... - - - - - - - -
-
-
- - Core -
-
- -
-
-
- - - Core... - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst... - - - - - - - -
-
-
- mem_rd_i -
-
-
- - - mem_rd_i - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - - - -
-
-
- - Instruction -
- Memory -
- -
-
-
- - - Instruction... - - - - - - - -
-
-
- - A - -
-
-
- - - A - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - -
-
-
-

- - - 32 -
- / - - -

-
-
-
- - - 32... - - - - - - - -
-
-
- - instr_i - -
-
-
- - - instr_i - - - - - - - -
-
-
- mem_size_o -
-
-
- - - mem_size_o - - - - - - - -
-
-
-

- - - / - - -

-

- - - 32 - - -

-
-
-
- - - /... - - - - - - - -
-
-
- - instr_addr - -
-
-
- - - instr_addr - - - - - - - -
-
-
- - instr - -
-
-
- - - instr - - - - - - - -
-
-
- mem_we_o -
-
-
- - - mem_we_o - - - - - - - -
-
-
- mem_req_o -
-
-
- - - mem_req_o - - - - - - - -
-
-
- mem_wd_o -
-
-
- - - mem_wd_o - - - - - - - -
-
-
- mem_addr_o -
-
-
- - - mem_addr_o - - - - - - - -
-
-
- instr_addr_o -
-
-
- - - instr_addr_o - - - - - - - - - -
-
-
- 3 -
-
-
- - - 3 - - - - - - - -
-
-
- stall_i -
-
-
- - - stall... - - - - - - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- core_req_i -
-
-
- - - core_req_i - - - - - - - -
-
-
- core_we_i -
-
-
- - - core_we_i - - - - - - - -
-
-
- core_size_i -
-
-
- - - core_size_i - - - - - - - -
-
-
- core_wd_i -
-
-
- - - core_wd_i - - - - - - - -
-
-
- core_addr_i -
-
-
- - - core_addr_i - - - - - - - - -
-
-
- core_stall_o -
-
-
- - - core_stall_o - - - - - - - -
-
-
- core_rd_o -
-
-
- - - core_rd_o - - - - - - - -
-
-
- mem_wd_o -
-
-
- - - mem_wd_o - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- mem_be_o -
-
-
- - - mem_be_o - - - - - - - -
-
-
- mem_we_o -
-
-
- - - mem_we_o - - - - - - - -
-
-
- mem_req_o -
-
-
- - - mem_req_o - - - - - - - -
-
-
- mem_ready_i -
-
-
- - - mem_ready_i - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- mem_addr_o -
-
-
- - - mem_addr_o - - - - - - - - - - - - -
-
-
- mem_rd_i -
-
-
- - - mem_rd_i - - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - - -
-
-
- 4 -
-
-
- - - 4 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - -
-
-
- - Data -
- Memory -
- -
-
-
- - - Data... - - - - - - - -
-
-
- - A - -
-
-
- - - A - - - - - - - -
-
-
- - WE - -
-
-
- - - WE - - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - -
-
-
- - WD - -
-
-
- - - WD - - - - - - - -
-
-
- BE -
-
-
- - - BE - - - - - - - - - -
-
-
-

- - 8 - - - -
- - / - - - -

-
-
-
- - - 8... - - - - - - - -
-
-
- out [0] -
-
-
- - - out [0] - - - - - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - - -
-
-
- [31:24] -
-
-
- - - [31:24] - - - - - - - -
-
-
- {8'd0,[23:0]} -
-
-
- - - {8'd0,[23:0... - - - - - - - -
-
-
- - Periph -
- Device -
- 1 -
- -
-
-
- - - Periph... - - - - - - - - - -
-
-
- - A - -
-
-
- - - A - - - - - - - - - -
-
-
- - WE - -
-
-
- - - WE - - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - - - -
-
-
- - WD - -
-
-
- - - WD - - - - - - - -
-
-
- out [1] -
-
-
- - - out [1] - - - - - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - - -
-
-
- - Periph -
- Device -
- 255 -
- -
-
-
- - - Periph... - - - - - - - -
-
-
- - A - -
-
-
- - - A - - - - - - - -
-
-
- - WE - -
-
-
- - - WE - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - -
-
-
- - WD - -
-
-
- - - WD - - - - - - - -
-
-
- out [255] -
-
-
- - - out [255] - - - - - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - - - - - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - -
-
-
- - OneHot Encoder - -
-
-
- - - OneHot Encoder - - - - - - - -
-
-
- in -
-
-
- - - in - - - - - - - -
-
-
- out -
-
-
- - - out - - - - - - - -
-
-
-

- - - 256 -
- - / - - - -

-
-
-
- - - 256... - - - - - - - - - - - - - -
-
-
-
- 0 -
-
-
-
- - - 0 - - - - - - - -
-
-
- 1 -
-
-
- - - 1 - - - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- — -
-
-
- - - — - - - - - - - - -
-
-
- 1'b1 -
-
-
- - - 1'b1 - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst... - - - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst... - - - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst... - - - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +
clk_i
clk_i

rst_i

rst_i
input signals
input signals
255
255
req
req
internal signal broken for schematic readability
internal signal broken...
—
—
LOAD/
STORE
UNIT
LOAD/...
Core

Core...
rst_i
rst...
mem_rd_i
mem_rd_i
clk_i
clk_i
Instruction
Memory
Instruction...
A
A
RD
RD

32
/

32...
instr_i
instr_i
mem_size_o
mem_size_o

/

32

/...
instr_addr
instr_addr
instr
instr
mem_we_o
mem_we_o
mem_req_o
mem_req_o
mem_wd_o
mem_wd_o
mem_addr_o
mem_addr_o
instr_addr_o
instr_addr_o
3
3
stall_i
stall...
32
32
32
32
core_req_i
core_req_i
core_we_i
core_we_i
core_size_i
core_size_i
core_wd_i
core_wd_i
core_addr_i
core_addr_i
core_stall_o
core_stall_o
core_rd_o
core_rd_o
mem_wd_o
mem_wd_o
32
32
mem_be_o
mem_be_o
mem_we_o
mem_we_o
mem_req_o
mem_req_o
mem_ready_i
mem_ready_i
clk_i
clk_i
mem_addr_o
mem_addr_o
mem_rd_i
mem_rd_i

rst_i

rst_i
4
4
32
32
32
32
32
32
Data
Memory
Data...
A
A
WE
WE
RD
RD
clk_i
clk_i
req
req
WD
WD
BE
BE

8
/

8...
out [0]
out [0]
req
req
[31:24]
[31:24]
{8'd0,[23:0]}
{8'd0,[23:0...
Periph
Device
1
Periph...
A
A
WE
WE
RD
RD
clk_i
clk_i
req
req
WD
WD
out [1]
out [1]
req
req
Periph
Device
255
Periph...
A
A
WE
WE
RD
RD
clk_i
clk_i
req
req
WD
WD
out [255]
out [255]
req
req
req
req
OneHot Encoder
OneHot Encoder
in
in
out
out

256
/

256...
0
0
1
1
32
32
32
32
32
32
32
32
—
—
1'b1
1'b1
rst_i
rst...

rst_i

rst_i
rst_i
rst...

rst_i

rst_i
rst_i
rst...

rst_i

rst_iText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Labs/lab_13_periph/tab_01.png b/.pic/Labs/lab_13_periph/tab_01.png index 5e4f0c8..3aa3e5a 100644 Binary files a/.pic/Labs/lab_13_periph/tab_01.png and b/.pic/Labs/lab_13_periph/tab_01.png differ diff --git a/.pic/Labs/lab_13_periph/tab_01.xlsx b/.pic/Labs/lab_13_periph/tab_01.xlsx index 5e76273..7b339b3 100644 Binary files a/.pic/Labs/lab_13_periph/tab_01.xlsx and b/.pic/Labs/lab_13_periph/tab_01.xlsx differ diff --git a/.pic/Labs/lab_13_periph/tab_08.png b/.pic/Labs/lab_13_periph/tab_08.png index 94b9446..733992e 100644 Binary files a/.pic/Labs/lab_13_periph/tab_08.png and b/.pic/Labs/lab_13_periph/tab_08.png differ diff --git a/.pic/Labs/lab_13_periph/tab_08.xlsx b/.pic/Labs/lab_13_periph/tab_08.xlsx index bf458fd..7d7bc49 100644 Binary files a/.pic/Labs/lab_13_periph/tab_08.xlsx and b/.pic/Labs/lab_13_periph/tab_08.xlsx differ diff --git a/.pic/Labs/lab_15_programming_device/fig_04.drawio.svg b/.pic/Labs/lab_15_programming_device/fig_04.drawio.svg index 605bb47..496be99 100644 --- a/.pic/Labs/lab_15_programming_device/fig_04.drawio.svg +++ b/.pic/Labs/lab_15_programming_device/fig_04.drawio.svg @@ -1,2563 +1,4 @@ - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - -
-
-
- - входные сигналы - -
-
-
- - - входные сигналы - - - - - - - - - - - -
-
-
- 255 -
-
-
- - - 255 - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - -
-
-
-
- - внутренний сигнал, оборванный для улучшения читаемости схемы - -
-
-
-
-
- - - внутренний сигнал, оборванный для улучшения читаемости схемы - - - - - - - -
-
-
- — -
-
-
- - - — - - - - - - - -
-
-
- LOAD/ -
- STORE -
- UNIT -
-
-
- - - LOAD/... - - - - - - - -
-
-
- - Core -
-
- -
-
-
- - - Core... - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst... - - - - - - - -
-
-
- mem_rd_i -
-
-
- - - mem_rd_i - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - - -
-
-
- - Instruction -
- Memory -
- -
-
-
- - - Instruction... - - - - - - - -
-
-
- RA -
-
-
- - - RA - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - -
-
-
- - instr_i - -
-
-
- - - instr_i - - - - - - - -
-
-
- mem_size_o -
-
-
- - - mem_size_o - - - - - - - -
-
-
- - instr_addr - -
-
-
- - - instr_addr - - - - - - - -
-
-
- - instr - -
-
-
- - - instr - - - - - - - -
-
-
- mem_we_o -
-
-
- - - mem_we_o - - - - - - - -
-
-
- mem_req_o -
-
-
- - - mem_req_o - - - - - - - -
-
-
- mem_wd_o -
-
-
- - - mem_wd_o - - - - - - - -
-
-
- mem_addr_o -
-
-
- - - mem_addr_o - - - - - - - -
-
-
- instr_addr_o -
-
-
- - - instr_addr_o - - - - - - - - - -
-
-
- 3 -
-
-
- - - 3 - - - - - - - -
-
-
- stall_i -
-
-
- - - stall... - - - - - - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- core_req_i -
-
-
- - - core_req_i - - - - - - - -
-
-
- core_we_i -
-
-
- - - core_we_i - - - - - - - -
-
-
- core_size_i -
-
-
- - - core_size_i - - - - - - - -
-
-
- core_wd_i -
-
-
- - - core_wd_i - - - - - - - -
-
-
- core_addr_i -
-
-
- - - core_addr_i - - - - - - - - -
-
-
- core_stall_o -
-
-
- - - core_stall_o - - - - - - - -
-
-
- core_rd_o -
-
-
- - - core_rd_o - - - - - - - -
-
-
- mem_wd_o -
-
-
- - - mem_wd_o - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- mem_be_o -
-
-
- - - mem_be_o - - - - - - - -
-
-
- mem_we_o -
-
-
- - - mem_we_o - - - - - - - -
-
-
- mem_req_o -
-
-
- - - mem_req_o - - - - - - - -
-
-
- mem_ready_i -
-
-
- - - mem_ready_i - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- mem_addr_o -
-
-
- - - mem_addr_o - - - - - - - - - - - -
-
-
- mem_rd_i -
-
-
- - - mem_rd_i - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - -
-
-
- - Data -
- Memory -
- -
-
-
- - - Data... - - - - - - - -
-
-
- - A - -
-
-
- - - A - - - - - - - -
-
-
- - WE - -
-
-
- - - WE - - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - -
-
-
- - WD - -
-
-
- - - WD - - - - - - - -
-
-
- BE -
-
-
- - - BE - - - - - - - - - -
-
-
-

- - 8 - - - -
- - / - - - -

-
-
-
- - - 8... - - - - - - - -
-
-
- out [0] -
-
-
- - - out [0] - - - - - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - - -
-
-
- [31:24] -
-
-
- - - [31:24] - - - - - - - -
-
-
- {8'd0,[23:0]} -
-
-
- - - {8'd0,[23:0... - - - - - - - -
-
-
- - Periph -
- Device -
- 1 -
- -
-
-
- - - Periph... - - - - - - - - - -
-
-
- - A - -
-
-
- - - A - - - - - - - - - -
-
-
- - WE - -
-
-
- - - WE - - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - - - -
-
-
- - WD - -
-
-
- - - WD - - - - - - - -
-
-
- out [1] -
-
-
- - - out [1] - - - - - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - - -
-
-
- - Periph -
- Device -
- 255 -
- -
-
-
- - - Periph... - - - - - - - -
-
-
- - A - -
-
-
- - - A - - - - - - - -
-
-
- - WE - -
-
-
- - - WE - - - - - - - -
-
-
- - RD - -
-
-
- - - RD - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - -
-
-
- - WD - -
-
-
- - - WD - - - - - - - -
-
-
- out [255] -
-
-
- - - out [255] - - - - - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - - - - - - - - - - - -
-
-
- - OneHot Encoder - -
-
-
- - - OneHot Encoder - - - - - - - -
-
-
- in -
-
-
- - - in - - - - - - - -
-
-
- out -
-
-
- - - out - - - - - - - -
-
-
-

- - - 256 -
- - / - - - -

-
-
-
- - - 256... - - - - - - - - - - - - - -
-
-
-
- 0 -
-
-
-
- - - 0 - - - - - - - -
-
-
- 1 -
-
-
- - - 1 - - - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- — -
-
-
- - - — - - - - - - - - -
-
-
- 1'b1 -
-
-
- - - 1'b1 - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst... - - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst... - - - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst... - - - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - -
-
-
-
- - Bluster - -
-
-
-
- - - Bluster - - - - - - - - - -
-
-
- - - clk_i - - -
-
-
- - - clk_i - - - - - - - -
-
-
- - rst_i - -
-
-
- - - rst... - - - - - - - - - -
-
-
-

- - - rst_i - - -

-
-
-
- - - rst_i - - - - - - - - -
-
-
- instr_wdata_o -
-
-
- - - instr_wdata... - - - - - - - - -
-
-
- instr_addr_o -
-
-
- - - instr_addr_o - - - - - - - -
-
-
- instr_we_o -
-
-
- - - instr_we_o - - - - - - - -
-
-
- data_wdata_o -
-
-
- - - data_wdata_o - - - - - - - -
-
-
- data_addr_o -
-
-
- - - data_addr_o - - - - - - - -
-
-
- data_we_o -
-
-
- - - data_we_o - - - - - - - - -
-
-
- tx_o -
-
-
- - - tx_o - - - - - - - -
-
-
- WE -
-
-
- - - WE - - - - - - - -
-
-
- WA -
-
-
- - - WA - - - - - - - -
-
-
- WD -
-
-
- - - WD - - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- core_reset_o -
-
-
- - - core_reset_o - - - - - - - - - -
-
-
- 4 -
-
-
- - - 4 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - -
-
-
- req -
-
-
- - - req - - - - - - - -
-
-
-
- - 1 - -
-
- - 0 - -
- - -
-
-
-
- - - 1... - - - - - - - -
-
-
-
- - 1 - -
-
- - 0 - -
- - -
-
-
-
- - - 1... - - - - - - - -
-
-
-
- - 1 - -
-
- - 0 - -
- - -
-
-
-
- - - 1... - - - - - - - -
-
-
-
- - 1 - -
-
- - 0 - -
- - -
-
-
-
- - - 1... - - - - - - - -
-
-
-
- - 1 - -
-
- - 0 - -
- - -
-
-
-
- - - 1... - - - - - - - - - - - - - - - -
-
-
- 4'hf -
-
-
- - - 4'hf - - - - - - - - - - - - -
-
-
- - tx_o - -
-
-
- - - tx_o - - - - - - - - -
-
-
- - rx_i - -
-
-
- - - rx_i - - - - - - - -
-
-
-

- - - rx_i - - -

-
-
-
- - - rx_i - - - - - - - -
-
-
- tx_o -
-
-
- - - tx_o - - - - - - - -
-
-
- — -
-
-
- - - — - - - - - - - -
-
-
- выходной сигнал -
-
-
- - - выходной сигнал - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +

rst_i

rst_i
clk_i
clk_i

rst_i

rst_i
input signals
input signals
255
255
req
req
Internal signal broken for readability
Internal signal broken...
—
—
LOAD/
STORE
UNIT
LOAD/...
Core

Core...
rst_i
rst...
mem_rd_i
mem_rd_i
clk_i
clk_i
Instruction
Memory
Instruction...
RA
RA
RD
RD
instr_i
instr_i
mem_size_o
mem_size_o
instr_addr
instr_addr
instr
instr
mem_we_o
mem_we_o
mem_req_o
mem_req_o
mem_wd_o
mem_wd_o
mem_addr_o
mem_addr_o
instr_addr_o
instr_addr_o
3
3
stall_i
stall...
32
32
32
32
core_req_i
core_req_i
core_we_i
core_we_i
core_size_i
core_size_i
core_wd_i
core_wd_i
core_addr_i
core_addr_i
core_stall_o
core_stall_o
core_rd_o
core_rd_o
mem_wd_o
mem_wd_o
32
32
mem_be_o
mem_be_o
mem_we_o
mem_we_o
mem_req_o
mem_req_o
mem_ready_i
mem_ready_i
clk_i
clk_i
mem_addr_o
mem_addr_o
mem_rd_i
mem_rd_i
32
32
Data
Memory
Data...
A
A
WE
WE
RD
RD
clk_i
clk_i
req
req
WD
WD
BE
BE

8
/

8...
out [0]
out [0]
req
req
[31:24]
[31:24]
{8'd0,[23:0]}
{8'd0,[23:0...
Periph
Device
1
Periph...
A
A
WE
WE
RD
RD
clk_i
clk_i
req
req
WD
WD
out [1]
out [1]
req
req
Periph
Device
255
Periph...
A
A
WE
WE
RD
RD
clk_i
clk_i
req
req
WD
WD
out [255]
out [255]
req
req
OneHot Encoder
OneHot Encoder
in
in
out
out

256
/

256...
0
0
1
1
32
32
32
32
32
32
32
32
—
—
1'b1
1'b1
rst_i
rst...
rst_i
rst...

rst_i

rst_i
rst_i
rst...

rst_i

rst_i
Bluster
Bluster
clk_i
clk_i
rst_i
rst...

rst_i

rst_i
instr_wdata_o
instr_wdata...
instr_addr_o
instr_addr_o
instr_we_o
instr_we_o
data_wdata_o
data_wdata_o
data_addr_o
data_addr_o
data_we_o
data_we_o
tx_o
tx_o
WE
WE
WA
WA
WD
WD
32
32
32
32
32
32
32
32
core_reset_o
core_reset_o
4
4
32
32
32
32
req
req
1
0
1...
1
0
1...
1
0
1...
1
0
1...
1
0
1...
4'hf
4'hf
tx_o
tx_o
rx_i
rx_i

rx_i

rx_i
tx_o
tx_o
—
—
output signal
output signalText is not SVG - cannot display \ No newline at end of file diff --git a/.pic/Other/rv32i/example_instr_code.png b/.pic/Other/rv32i/example_instr_code.png index b75ad14..adc2159 100644 Binary files a/.pic/Other/rv32i/example_instr_code.png and b/.pic/Other/rv32i/example_instr_code.png differ diff --git a/.pic/Other/rv32i/example_instr_code.xlsx b/.pic/Other/rv32i/example_instr_code.xlsx index 9b1e119..3f0d632 100644 Binary files a/.pic/Other/rv32i/example_instr_code.xlsx and b/.pic/Other/rv32i/example_instr_code.xlsx differ diff --git a/.pic/Other/rv32i/fig_01.drawio.svg b/.pic/Other/rv32i/fig_01.drawio.svg index 069a41d..c597f36 100644 --- a/.pic/Other/rv32i/fig_01.drawio.svg +++ b/.pic/Other/rv32i/fig_01.drawio.svg @@ -1,589 +1,4 @@ - - - - - - - - - - Регистровый файл - - - - - - - - - -
-
-
- x0 -
-
-
- - - x0 - - - - - - - - -
-
-
- 000000....0 -
-
-
- - - 000000....0 - - - - - - - - - - -
-
-
- x1 -
-
-
- - - x1 - - - - - - - - -
-
-
- 100110...0 -
-
-
- - - 100110...0 - - - - - - - - - - -
-
-
- x2 -
-
-
- - - x2 - - - - - - - - - - - - -
-
-
- - . -
- . -
- . - -
-
-
- - - .... - - - - - - - - -
-
-
- 32-битные слова -
-
-
- - - 32-битные слова - - - - - - - - - - -
-
-
- x31 -
-
-
- - - x31 - - - - - - - - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - -
-
-
- clk -
-
-
- - - clk - - - - - - - - -
-
-
- - Программный счётчик - -
-
-
- - - Программный счётчик - - - - - - -
-
-
- - Основная память - -
-
-
- - - Основная память - - - - - - - -
-
-
- АЛУ -
-
-
- - - АЛУ - - - - - - - - - - - -
-
-
- - Регистры контроля и статуса - -
-
-
- - - Регистры контроля и статуса - - - - - - - - - - -
-
-
- 0 -
-
-
- - - 0 - - - - - - - - - -
-
-
- 4 -
-
-
- - - 4 - - - - - - - - - -
-
-
- 8 -
-
-
- - - 8 - - - - - - - - - - - -
-
-
- 32-битные слова -
-
-
- - - 32-битные слова - - - - - - - - - - - -
-
-
- 31 -
-
-
- - - 31 - - - - - - -
-
-
- 0 -
-
-
- - - 0 - - - - - - -
-
-
- - Адрес - -
-
-
- - - Адрес - - - - - - - - - - - -
-
-
- 0 -
-
-
- - - 0 - - - - - - - - - -
-
-
- 4 -
-
-
- - - 4 - - - - - - - - - -
-
-
- 8 -
-
-
- - - 8 - - - - - - - - - - - -
-
-
- 32-битные слова -
-
-
- - - 32-битные слова - - - - - - - - - - - -
-
-
- 31 -
-
-
- - - 31 - - - - - - -
-
-
- 0 -
-
-
- - - 0 - - - - - - -
-
-
- - Адрес - -
-
-
- - - Адрес - - - - - - -
-
-
- 32 -
-
-
- - - 32 - - - - - - - - - - Text is not SVG - cannot display - - - - \ No newline at end of file + + + +Register file
x0
x0
000000....0
000000....0
x1
x1
100110...0
100110...0
x2
x2
.
.
.
....
32-bit words
32-bit words
x31
x31
32
32
clk
clk
Program
counter
Program...
Main
Memory
Main...
ALU
ALU
Control and status registers
Control and status...
0
0
4
4
8
8
32-bit words
32-bit words
31
31
0
0
Address
Address
0
0
4
4
8
8
32-bit words
32-bit words
31
31
0
0
Address
Address
32
32Text is not SVG - cannot display \ No newline at end of file