From 06da941d8aa057e9d620c01277d5352012b65158 Mon Sep 17 00:00:00 2001 From: Andrei Solodovnikov Date: Wed, 16 Sep 2026 16:44:51 +0300 Subject: [PATCH] Update lab_06.data_mem.sv --- Labs/Made-up modules/lab_06.data_mem.sv | 81 ++++--------------------- 1 file changed, 12 insertions(+), 69 deletions(-) diff --git a/Labs/Made-up modules/lab_06.data_mem.sv b/Labs/Made-up modules/lab_06.data_mem.sv index 118b98d..8b6c44e 100644 --- a/Labs/Made-up modules/lab_06.data_mem.sv +++ b/Labs/Made-up modules/lab_06.data_mem.sv @@ -8,8 +8,7 @@ See https://github.com/MPSU/APS/blob/master/LICENSE file for licensing details. * ------------------------------------------------------------------------------ */ - -module data_mem( +module data_mem ( input logic clk_i, input logic mem_req_i, input logic write_enable_i, @@ -23,78 +22,22 @@ assign ready_o = 1'b1; import memory_pkg::DATA_MEM_SIZE_WORDS; logic [31:0] ram [DATA_MEM_SIZE_WORDS]; +logic [31:0] addr; +assign addr = addr_i[2+:$clog2(DATA_MEM_SIZE_WORDS)]; + always_ff @(posedge clk_i) begin - case(1) - !mem_req_i||write_enable_i: read_data_o <= read_data_o; - default: read_data_o <= ram[addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]]; - endcase + if(mem_req_i & !write_enable_i) begin + read_data_o <= ram[addr]; + end end always_ff @(posedge clk_i) begin - case({mem_req_i, write_enable_i, byte_enable_i}) - 6'd49: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [7:0] <= write_data_i[7:0]; + if(mem_req_i & write_enable_i) begin + if(byte_enable_i[0]) ram[addr][ 7: 0] = write_data_i[ 7: 0]; + if(byte_enable_i[1]) ram[addr][15: 8] = write_data_i[15: 8]; + if(byte_enable_i[2]) ram[addr][23:16] = write_data_i[23:16]; + if(byte_enable_i[3]) ram[addr][31:24] = write_data_i[31:24]; end - 6'd50: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [15:8] <= write_data_i[15:8]; - end - 6'd51: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [7:0] <= write_data_i[7:0]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [15:8] <= write_data_i[15:8]; - end - 6'd52: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [23:16] <= write_data_i[23:16]; - end - 6'd53: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [7:0] <= write_data_i[7:0]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [23:16] <= write_data_i[23:16]; - end - 6'd54: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [15:8] <= write_data_i[15:8]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [23:16] <= write_data_i[23:16]; - end - 6'd55: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [7:0] <= write_data_i[7:0]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [15:8] <= write_data_i[15:8]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [23:16] <= write_data_i[23:16]; - end - 6'd56: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [31:24] <= write_data_i[31:24]; - end - 6'd57: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [7:0] <= write_data_i[7:0]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [31:24] <= write_data_i[31:24]; - end - 6'd58: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [15:8] <= write_data_i[15:8]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [31:24] <= write_data_i[31:24]; - end - 6'd59: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [7:0] <= write_data_i[7:0]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [15:8] <= write_data_i[15:8]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [31:24] <= write_data_i[31:24]; - end - 6'd60: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [23:16] <= write_data_i[23:16]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [31:24] <= write_data_i[31:24]; - end - 6'd61: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [7:0] <= write_data_i[7:0]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [23:16] <= write_data_i[23:16]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [31:24] <= write_data_i[31:24]; - end - 6'd62: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [15:8] <= write_data_i[15:8]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [23:16] <= write_data_i[23:16]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [31:24] <= write_data_i[31:24]; - end - 6'd63: begin - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [7:0] <= write_data_i[7:0]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [15:8] <= write_data_i[15:8]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [23:16] <= write_data_i[23:16]; - ram [addr_i[32'ha&32'h2+:$clog2(DATA_MEM_SIZE_WORDS)]] [31:24] <= write_data_i[31:24]; - end - endcase end endmodule